[llvm-commits] [llvm] r123837 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/arm_instructions.s
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Wed Jan 19 08:56:52 PST 2011
Author: bruno
Date: Wed Jan 19 10:56:52 2011
New Revision: 123837
URL: http://llvm.org/viewvc/llvm-project?rev=123837&view=rev
Log:
Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/test/MC/ARM/arm_instructions.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=123837&r1=123836&r2=123837&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Jan 19 10:56:52 2011
@@ -3745,28 +3745,28 @@
let Inst{19-16} = CRn;
}
-def MCRR : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc,
+def MCRR : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
- NoItinerary, "mcrr", "\t$cop, $opc, $Rt, $Rt2, $CRm",
+ NoItinerary, "mcrr", "\t$cop, $opc1, $Rt, $Rt2, $CRm",
[/* For disassembly only; pattern left blank */]> {
let Inst{23-20} = 0b0100;
bits<4> Rt;
bits<4> Rt2;
bits<4> cop;
- bits<3> opc1;
+ bits<4> opc1;
bits<4> CRm;
let Inst{15-12} = Rt;
let Inst{19-16} = Rt2;
let Inst{11-8} = cop;
- let Inst{7-5} = opc1;
+ let Inst{7-4} = opc1;
let Inst{3-0} = CRm;
}
-def MCRR2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc,
+def MCRR2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
- NoItinerary, "mcrr2\t$cop, $opc, $Rt, $Rt2, $CRm",
+ NoItinerary, "mcrr2\t$cop, $opc1, $Rt, $Rt2, $CRm",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111;
let Inst{23-20} = 0b0100;
@@ -3774,38 +3774,38 @@
bits<4> Rt;
bits<4> Rt2;
bits<4> cop;
- bits<3> opc1;
+ bits<4> opc1;
bits<4> CRm;
let Inst{15-12} = Rt;
let Inst{19-16} = Rt2;
let Inst{11-8} = cop;
- let Inst{7-5} = opc1;
+ let Inst{7-4} = opc1;
let Inst{3-0} = CRm;
}
-def MRRC : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc,
+def MRRC : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
- NoItinerary, "mrrc", "\t$cop, $opc, $Rt, $Rt2, $CRm",
+ NoItinerary, "mrrc", "\t$cop, $opc1, $Rt, $Rt2, $CRm",
[/* For disassembly only; pattern left blank */]> {
let Inst{23-20} = 0b0101;
bits<4> Rt;
bits<4> Rt2;
bits<4> cop;
- bits<3> opc1;
+ bits<4> opc1;
bits<4> CRm;
let Inst{15-12} = Rt;
let Inst{19-16} = Rt2;
let Inst{11-8} = cop;
- let Inst{7-5} = opc1;
+ let Inst{7-4} = opc1;
let Inst{3-0} = CRm;
}
-def MRRC2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc,
+def MRRC2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
- NoItinerary, "mrrc2\t$cop, $opc, $Rt, $Rt2, $CRm",
+ NoItinerary, "mrrc2\t$cop, $opc1, $Rt, $Rt2, $CRm",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111;
let Inst{23-20} = 0b0101;
@@ -3813,13 +3813,13 @@
bits<4> Rt;
bits<4> Rt2;
bits<4> cop;
- bits<3> opc1;
+ bits<4> opc1;
bits<4> CRm;
let Inst{15-12} = Rt;
let Inst{19-16} = Rt2;
let Inst{11-8} = cop;
- let Inst{7-5} = opc1;
+ let Inst{7-4} = opc1;
let Inst{3-0} = CRm;
}
Modified: llvm/trunk/test/MC/ARM/arm_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=123837&r1=123836&r2=123837&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/arm_instructions.s (original)
+++ llvm/trunk/test/MC/ARM/arm_instructions.s Wed Jan 19 10:56:52 2011
@@ -135,3 +135,22 @@
isb
@ CHECK: mrs r8, cpsr @ encoding: [0x00,0x80,0x0f,0xe1]
mrs r8, cpsr
+
+@ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xee]
+ mcr p7, #1, r5, c1, c1, #4
+@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee]
+ mrc p14, #0, r1, c1, c2, #4
+@ CHECK: mcrr p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x44,0xec]
+ mcrr p7, #1, r5, r4, c1
+@ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xec]
+ mrrc p7, #1, r5, r4, c1
+
+@ CHECK: mcr2 p7, #1, r5, c1, c1, #4 @ encoding: [0x91,0x57,0x21,0xfe]
+ mcr2 p7, #1, r5, c1, c1, #4
+@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
+ mrc2 p14, #0, r1, c1, c2, #4
+@ CHECK: mcrr2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x44,0xfc]
+ mcrr2 p7, #1, r5, r4, c1
+@ CHECK: mrrc2 p7, #1, r5, r4, c1 @ encoding: [0x11,0x57,0x54,0xfc]
+ mrrc2 p7, #1, r5, r4, c1
+
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