[llvm-commits] [llvm] r123783 - in /llvm/trunk: lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/ARMRegisterInfo.td test/MC/ARM/simple-fp-encoding.s test/MC/ARM/thumb2.s
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Tue Jan 18 13:58:21 PST 2011
Author: bruno
Date: Tue Jan 18 15:58:20 2011
New Revision: 123783
URL: http://llvm.org/viewvc/llvm-project?rev=123783&view=rev
Log:
Create two new generic classes to represent the following VMRS/VMSR variations:
vmrs reg, fpexc
vmrs reg, fpsid
vmsr fpexc, reg
vmsr fpsid, reg
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
llvm/trunk/test/MC/ARM/simple-fp-encoding.s
llvm/trunk/test/MC/ARM/thumb2.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=123783&r1=123782&r2=123783&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Jan 18 15:58:20 2011
@@ -870,38 +870,19 @@
} // neverHasSideEffects
//===----------------------------------------------------------------------===//
-// Misc.
+// Move from VFP System Register to ARM core register.
//
-// APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
-// to APSR.
-let Defs = [CPSR], Uses = [FPSCR] in
-def FMSTAT : VFPAI<(outs), (ins), VFPMiscFrm, IIC_fpSTAT,
- "vmrs", "\tapsr_nzcv, fpscr",
- [(arm_fmstat)]> {
- let Inst{27-20} = 0b11101111;
- let Inst{19-16} = 0b0001;
- let Inst{15-12} = 0b1111;
- let Inst{11-8} = 0b1010;
- let Inst{7} = 0;
- let Inst{6-5} = 0b00;
- let Inst{4} = 1;
- let Inst{3-0} = 0b0000;
-}
+class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
+ list<dag> pattern>:
+ VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
-// FPSCR <-> GPR
-let hasSideEffects = 1, Uses = [FPSCR] in
-def VMRS : VFPAI<(outs GPR:$Rt), (ins), VFPMiscFrm, IIC_fpSTAT,
- "vmrs", "\t$Rt, fpscr",
- [(set GPR:$Rt, (int_arm_get_fpscr))]> {
// Instruction operand.
bits<4> Rt;
- // Encode instruction operand.
- let Inst{15-12} = Rt;
-
let Inst{27-20} = 0b11101111;
- let Inst{19-16} = 0b0001;
+ let Inst{19-16} = opc19_16;
+ let Inst{15-12} = Rt;
let Inst{11-8} = 0b1010;
let Inst{7} = 0;
let Inst{6-5} = 0b00;
@@ -909,10 +890,34 @@
let Inst{3-0} = 0b0000;
}
-let Defs = [FPSCR] in
-def VMSR : VFPAI<(outs), (ins GPR:$src), VFPMiscFrm, IIC_fpSTAT,
- "vmsr", "\tfpscr, $src",
- [(int_arm_set_fpscr GPR:$src)]> {
+// APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
+// to APSR.
+let Defs = [CPSR], Uses = [FPSCR], Rt = 0b1111 /* apsr_nzcv */ in
+def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
+ "vmrs", "\tapsr_nzcv, fpscr", [(arm_fmstat)]>;
+
+// Application level FPSCR -> GPR
+let hasSideEffects = 1, Uses = [FPSCR] in
+def VMRS : MovFromVFP<0b0001 /* fpscr */, (outs GPR:$Rt), (ins),
+ "vmrs", "\t$Rt, fpscr",
+ [(set GPR:$Rt, (int_arm_get_fpscr))]>;
+
+// System level FPEXC, FPSID -> GPR
+let Uses = [FPSCR] in {
+ def VMRS_FPEXC : MovFromVFP<0b1000 /* fpexc */, (outs GPR:$Rt), (ins),
+ "vmrs", "\t$Rt, fpexc", []>;
+ def VMRS_FPSID : MovFromVFP<0b0000 /* fpsid */, (outs GPR:$Rt), (ins),
+ "vmrs", "\t$Rt, fpsid", []>;
+}
+
+//===----------------------------------------------------------------------===//
+// Move from ARM core register to VFP System Register.
+//
+
+class MovToVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
+ list<dag> pattern>:
+ VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
+
// Instruction operand.
bits<4> src;
@@ -920,12 +925,28 @@
let Inst{15-12} = src;
let Inst{27-20} = 0b11101110;
- let Inst{19-16} = 0b0001;
+ let Inst{19-16} = opc19_16;
let Inst{11-8} = 0b1010;
let Inst{7} = 0;
let Inst{4} = 1;
}
+let Defs = [FPSCR] in {
+ // Application level GPR -> FPSCR
+ def VMSR : MovToVFP<0b0001 /* fpscr */, (outs), (ins GPR:$src),
+ "vmsr", "\tfpscr, $src", [(int_arm_set_fpscr GPR:$src)]>;
+ // System level GPR -> FPEXC
+ def VMSR_FPEXC : MovToVFP<0b1000 /* fpexc */, (outs), (ins GPR:$src),
+ "vmsr", "\tfpexc, $src", []>;
+ // System level GPR -> FPSID
+ def VMSR_FPSID : MovToVFP<0b0000 /* fpsid */, (outs), (ins GPR:$src),
+ "vmsr", "\tfpsid, $src", []>;
+}
+
+//===----------------------------------------------------------------------===//
+// Misc.
+//
+
// Materialize FP immediates. VFP3 only.
let isReMaterializable = 1 in {
def FCONSTD : VFPAI<(outs DPR:$Dd), (ins vfp_f64imm:$imm),
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=123783&r1=123782&r2=123783&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Tue Jan 18 15:58:20 2011
@@ -201,6 +201,10 @@
def FPSCR : ARMReg<1, "fpscr">;
def ITSTATE : ARMReg<2, "itstate">;
+// Special Registers - only available in privileged mode.
+def FPSID : ARMReg<0, "fpsid">;
+def FPEXC : ARMReg<8, "fpexc">;
+
// Register classes.
//
// pc == Program Counter
Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-fp-encoding.s?rev=123783&r1=123782&r2=123783&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Tue Jan 18 15:58:20 2011
@@ -127,9 +127,17 @@
@ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee]
vmrs r0, fpscr
+@ CHECK: vmrs r0, fpexc @ encoding: [0x10,0x0a,0xf8,0xee]
+ vmrs r0, fpexc
+@ CHECK: vmrs r0, fpsid @ encoding: [0x10,0x0a,0xf0,0xee]
+ vmrs r0, fpsid
@ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
vmsr fpscr, r0
+@ CHECK: vmsr fpexc, r0 @ encoding: [0x10,0x0a,0xe8,0xee]
+ vmsr fpexc, r0
+@ CHECK: vmsr fpsid, r0 @ encoding: [0x10,0x0a,0xe0,0xee]
+ vmsr fpsid, r0
@ FIXME: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee]
@ vmov.f64 d16, #3.000000e+00
Modified: llvm/trunk/test/MC/ARM/thumb2.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2.s?rev=123783&r1=123782&r2=123783&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb2.s (original)
+++ llvm/trunk/test/MC/ARM/thumb2.s Tue Jan 18 15:58:20 2011
@@ -168,3 +168,16 @@
isb
@ CHECK: mrs r0, cpsr @ encoding: [0xef,0xf3,0x00,0x80]
mrs r0, cpsr
+@ CHECK: vmrs r0, fpscr @ encoding: [0xf1,0xee,0x10,0x0a]
+ vmrs r0, fpscr
+@ CHECK: vmrs r0, fpexc @ encoding: [0xf8,0xee,0x10,0x0a]
+ vmrs r0, fpexc
+@ CHECK: vmrs r0, fpsid @ encoding: [0xf0,0xee,0x10,0x0a]
+ vmrs r0, fpsid
+
+@ CHECK: vmsr fpscr, r0 @ encoding: [0xe1,0xee,0x10,0x0a]
+ vmsr fpscr, r0
+@ CHECK: vmsr fpexc, r0 @ encoding: [0xe8,0xee,0x10,0x0a]
+ vmsr fpexc, r0
+@ CHECK: vmsr fpsid, r0 @ encoding: [0xe0,0xee,0x10,0x0a]
+ vmsr fpsid, r0
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