[llvm-commits] [llvm] r123281 - in /llvm/trunk: lib/Target/Sparc/SparcInstrInfo.td test/CodeGen/SPARC/2011-01-11-CC.ll
Venkatraman Govindaraju
venkatra at cs.wisc.edu
Tue Jan 11 14:38:28 PST 2011
Author: venkatra
Date: Tue Jan 11 16:38:28 2011
New Revision: 123281
URL: http://llvm.org/viewvc/llvm-project?rev=123281&view=rev
Log:
SPARC backend: correct ICC/FCC uses for ADDX and SELECT_CC
Added:
llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll (with props)
Modified:
llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=123281&r1=123280&r2=123281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Tue Jan 11 16:38:28 2011
@@ -233,36 +233,39 @@
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
// instruction selection into a branch sequence. This has to handle all
// permutations of selection between i32/f32/f64 on ICC and FCC.
-let Uses = [ICC],
- usesCustomInserter = 1 in { // Expanded after instruction selection.
+ // Expanded after instruction selection.
+let Uses = [ICC], usesCustomInserter = 1 in {
def SELECT_CC_Int_ICC
: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
"; SELECT_CC_Int_ICC PSEUDO!",
[(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
imm:$Cond))]>;
+ def SELECT_CC_FP_ICC
+ : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_FP_ICC PSEUDO!",
+ [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
+ imm:$Cond))]>;
+
+ def SELECT_CC_DFP_ICC
+ : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
+ "; SELECT_CC_DFP_ICC PSEUDO!",
+ [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
+ imm:$Cond))]>;
+}
+
+let usesCustomInserter = 1, Uses = [FCC] in {
+
def SELECT_CC_Int_FCC
: Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
"; SELECT_CC_Int_FCC PSEUDO!",
[(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
imm:$Cond))]>;
-}
-let usesCustomInserter = 1, Uses = [FCC] in {
- def SELECT_CC_FP_ICC
- : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
- "; SELECT_CC_FP_ICC PSEUDO!",
- [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
- imm:$Cond))]>;
def SELECT_CC_FP_FCC
: Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
"; SELECT_CC_FP_FCC PSEUDO!",
[(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
imm:$Cond))]>;
- def SELECT_CC_DFP_ICC
- : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
- "; SELECT_CC_DFP_ICC PSEUDO!",
- [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
- imm:$Cond))]>;
def SELECT_CC_DFP_FCC
: Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
"; SELECT_CC_DFP_FCC PSEUDO!",
@@ -440,7 +443,8 @@
let Defs = [ICC] in
defm ADDCC : F3_12<"addcc", 0b010000, addc>;
-defm ADDX : F3_12<"addx", 0b001000, adde>;
+let Uses = [ICC] in
+ defm ADDX : F3_12<"addx", 0b001000, adde>;
// Section B.15 - Subtract Instructions, p. 110
defm SUB : F3_12 <"sub" , 0b000100, sub>;
Added: llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll?rev=123281&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll (added)
+++ llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll Tue Jan 11 16:38:28 2011
@@ -0,0 +1,76 @@
+; RUN: llc -march=sparc <%s | FileCheck %s
+
+
+define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind readnone noinline {
+entry:
+; CHECK: addcc
+; CHECK-NOT: subcc
+; CHECK: addx
+ %0 = add i64 %a, %b
+ %1 = icmp ugt i64 %0, %c
+ %2 = zext i1 %1 to i32
+ ret i32 %2
+}
+
+
+define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline {
+entry:
+; CHECK: test_select_int_icc
+; CHECK: subcc
+; CHECK: be
+ %0 = icmp eq i32 %a, 0
+ %1 = select i1 %0, i32 %b, i32 %c
+ ret i32 %1
+}
+
+
+define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline {
+entry:
+; CHECK: test_select_fp_icc
+; CHECK: subcc
+; CHECK: be
+ %0 = icmp eq i32 %a, 0
+ %1 = select i1 %0, float %f1, float %f2
+ ret float %1
+}
+
+define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
+entry:
+; CHECK: test_select_fp_icc
+; CHECK: subcc
+; CHECK: be
+ %0 = icmp eq i32 %a, 0
+ %1 = select i1 %0, double %f1, double %f2
+ ret double %1
+}
+
+define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline {
+entry:
+;CHECK: test_select_int_fcc
+;CHECK: fcmps
+;CHECK: fbne
+ %0 = fcmp une float %f, 0.000000e+00
+ %a.b = select i1 %0, i32 %a, i32 %b
+ ret i32 %a.b
+}
+
+
+define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline {
+entry:
+;CHECK: test_select_fp_fcc
+;CHECK: fcmps
+;CHECK: fbne
+ %0 = fcmp une float %f, 0.000000e+00
+ %1 = select i1 %0, float %f1, float %f2
+ ret float %1
+}
+
+define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline {
+entry:
+;CHECK: test_select_dfp_fcc
+;CHECK: fcmpd
+;CHECK: fbne
+ %0 = fcmp une double %f, 0.000000e+00
+ %1 = select i1 %0, double %f1, double %f2
+ ret double %1
+}
Propchange: llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll
------------------------------------------------------------------------------
svn:executable = *
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