[llvm-commits] [llvm] r123042 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Bob Wilson
bob.wilson at apple.com
Fri Jan 7 15:40:47 PST 2011
Author: bwilson
Date: Fri Jan 7 17:40:46 2011
New Revision: 123042
URL: http://llvm.org/viewvc/llvm-project?rev=123042&view=rev
Log:
Add an explanatory message for an assertion.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=123042&r1=123041&r2=123042&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jan 7 17:40:46 2011
@@ -3715,7 +3715,8 @@
// Since only 64-bit and 128-bit vectors are legal on ARM and
// we've eliminated the other cases...
- assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts);
+ assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
+ "unexpected vector sizes in ReconstructShuffle");
if (MaxElts[i] - MinElts[i] >= NumElts) {
// Span too large for a VEXT to cope
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