[llvm-commits] [PATCH] Remove unused variables found by gcc-4.6's -Wunused-but-set-variable (issue3827044)

[jyasskin at gmail.com]

Reviewers: ,

Description:
Some of these removals may actually indicate bugs, so someone who knows
this code better than I do should take a look.

There are a couple other gcc-4.6 warnings in googletest, but we should
get a fix for them when they release version 1.6.

Please review this at http://codereview.appspot.com/3827044/

Affected files:
   M     lib/Target/ARM/ARMFastISel.cpp
   M     lib/Target/ARM/ARMFrameInfo.cpp
   M     lib/Target/CellSPU/SPUISelLowering.cpp
   M     lib/Target/PowerPC/PPCISelLowering.cpp
   M     lib/Target/X86/X86ISelDAGToDAG.cpp


Index: lib/Target/X86/X86ISelDAGToDAG.cpp
===================================================================
--- lib/Target/X86/X86ISelDAGToDAG.cpp	(revision 122455)
+++ lib/Target/X86/X86ISelDAGToDAG.cpp	(working copy)
@@ -1604,13 +1604,13 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
      SDValue N0 = Node->getOperand(0);
      SDValue N1 = Node->getOperand(1);

-    unsigned LoReg, HiReg;
+    unsigned LoReg;
      switch (NVT.getSimpleVT().SimpleTy) {
      default: llvm_unreachable("Unsupported VT!");
-    case MVT::i8:  LoReg = X86::AL;  HiReg = X86::AH;  Opc = X86::MUL8r;  
break;
-    case MVT::i16: LoReg = X86::AX;  HiReg = X86::DX;  Opc = X86::MUL16r;  
break;
-    case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; Opc = X86::MUL32r;  
break;
-    case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; Opc = X86::MUL64r;  
break;
+    case MVT::i8:  LoReg = X86::AL;  Opc = X86::MUL8r; break;
+    case MVT::i16: LoReg = X86::AX;  Opc = X86::MUL16r; break;
+    case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
+    case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
      }

      SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,  
LoReg,
Index: lib/Target/CellSPU/SPUISelLowering.cpp
===================================================================
--- lib/Target/CellSPU/SPUISelLowering.cpp	(revision 122455)
+++ lib/Target/CellSPU/SPUISelLowering.cpp	(working copy)
@@ -683,10 +683,6 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPU
      // storage position offset from lower 16 byte aligned memory chunk
      SDValue offset = DAG.getNode(ISD::AND, dl, MVT::i32,
                                    basePtr, DAG.getConstant( 0xf, MVT::i32  
) );
-    // 16 - offset
-    SDValue offset_compl = DAG.getNode(ISD::SUB, dl, MVT::i32,
-                                        DAG.getConstant( 16, MVT::i32),
-                                        offset );
      // get a registerfull of ones. (this implementation is a workaround:  
LLVM
      // cannot handle 128 bit signed int constants)
      SDValue ones = DAG.getConstant(-1, MVT::v4i32 );
@@ -911,10 +907,6 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SP
      SDValue offset_compl = DAG.getNode(ISD::SUB, dl, MVT::i32,
                                             DAG.getConstant( 16, MVT::i32),
                                             offset);
-    SDValue hi_shift = DAG.getNode(ISD::SUB, dl, MVT::i32,
-                                      DAG.getConstant(  
VT.getSizeInBits()/8,
-                                                       MVT::i32),
-                                      offset_compl);
      // 16 - sizeof(Value)
      SDValue surplus = DAG.getNode(ISD::SUB, dl, MVT::i32,
                                       DAG.getConstant( 16, MVT::i32),
@@ -3260,4 +3252,3 @@ SPUTargetLowering::isLegalAddressingMode(const Add

    return false;
  }
-
Index: lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelLowering.cpp	(revision 122458)
+++ lib/Target/PowerPC/PPCISelLowering.cpp	(working copy)
@@ -1176,7 +1176,6 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue
  SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
                                               SelectionDAG &DAG) const {
    EVT PtrVT = Op.getValueType();
-  DebugLoc DL = Op.getDebugLoc();

    const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();

Index: lib/Target/ARM/ARMFrameInfo.cpp
===================================================================
--- lib/Target/ARM/ARMFrameInfo.cpp	(revision 122455)
+++ lib/Target/ARM/ARMFrameInfo.cpp	(working copy)
@@ -651,7 +651,6 @@ bool ARMFrameInfo::spillCalleeSavedRegisters(Machi

    MachineFunction &MF = *MBB.getParent();
    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
-  DebugLoc DL = MI->getDebugLoc();

    unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD :  
ARM::STMDB_UPD;
    unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE :  
ARM::STR_PRE;
@@ -673,7 +672,6 @@ bool ARMFrameInfo::restoreCalleeSavedRegisters(Mac
    MachineFunction &MF = *MBB.getParent();
    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
-  DebugLoc DL = MI->getDebugLoc();

    unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD :  
ARM::LDMIA_UPD;
    unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :  
ARM::LDR_POST;
Index: lib/Target/ARM/ARMFastISel.cpp
===================================================================
--- lib/Target/ARM/ARMFastISel.cpp	(revision 122455)
+++ lib/Target/ARM/ARMFastISel.cpp	(working copy)
@@ -1017,21 +1017,17 @@ bool ARMFastISel::SelectBranch(const Instruction *
          return false;

        unsigned CmpOpc;
-      unsigned CondReg;
        switch (VT.SimpleTy) {
          default: return false;
          // TODO: Verify compares.
          case MVT::f32:
            CmpOpc = ARM::VCMPES;
-          CondReg = ARM::FPSCR;
            break;
          case MVT::f64:
            CmpOpc = ARM::VCMPED;
-          CondReg = ARM::FPSCR;
            break;
          case MVT::i32:
            CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
-          CondReg = ARM::CPSR;
            break;
        }