[llvm-commits] [llvm] r122596 - /llvm/trunk/lib/CodeGen/StrongPHIElimination.cpp

[Jakob Stoklund Olesen]

On Dec 28, 2010, at 1:03 PM, Cameron Zwarich wrote:

> On Dec 28, 2010, at 12:55 PM, Jakob Stoklund Olesen wrote:
> 
>> On Dec 28, 2010, at 12:46 PM, Cameron Zwarich wrote:
>> 
>>> On Dec 28, 2010, at 11:14 AM, Bob Wilson wrote:
>>> 
>>>> On Dec 28, 2010, at 2:49 AM, Cameron Zwarich wrote:
>>>>> -    for (unsigned i = 0, e = BBI->getNumOperands(); i != e; ++i) {
>>>>> -      MachineOperand& MO = BBI->getOperand(i);
>>>>> -      if (!MO.isReg() || !MO.isDef())
>>>>> -        continue;
>>>>> +    for (MachineInstr::const_mop_iterator I = BBI->operands_begin(),
>>>>> +         E = BBI->operands_end(); I != E && I->isReg() && I->isDef(); ++I) {
>>>>> +      const MachineOperand& MO = *I;
>>>> 
>>>> This is relying on the register def operands being first.  I'm not sure that's always true.  OptionalDefOperands, like cc_out for ARM, may come later in the operand list.
>>> 
>>> Aren't optional defs only for physical registers? This code is only interested in defs of registers that appear in phis.
>> 
>> I wouldn't count on it, there are also variadic instructions.
>> 
>> Even if no current targets produce such instructions before register allocation, future targets might.
> 
> 
> What's the format of variadic instructions? Wouldn't all of the explicit defs appear at the front?

No, they look like:

  <fixed defs>, <fixed uses>, <variadic ops...>, <implicit ops>

The variadic operands can be uses or defs. For instance, ARM's LDM instructions have a variable number of defs.

/jakob

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