[llvm-commits] [llvm] r122364 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/conditional-indecrement.ll

[Chris Lattner]

On Dec 22, 2010, at 4:42 AM, Benjamin Kramer wrote:

> 
> On 22.12.2010, at 03:13, Chris Lattner wrote:
> 
>> 
>> On Dec 21, 2010, at 1:41 PM, Benjamin Kramer wrote:
>> 
>>> Author: d0k
>>> Date: Tue Dec 21 15:41:44 2010
>>> New Revision: 122364
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=122364&view=rev
>>> Log:
>>> Add some x86 specific dagcombines for conditional increments.
>>> 
>>> (add Y, (sete  X, 0)) -> cmp X, 1; adc  0, Y
>>> (add Y, (setne X, 0)) -> cmp X, 1; sbb -1, Y
>>> (sub (sete  X, 0), Y) -> cmp X, 1; sbb  0, Y
>>> (sub (setne X, 0), Y) -> cmp X, 1; adc -1, Y
>> 
>> Very nice.  Do we handle the cases when X and Y are the same value?  "X == 0 ? X+1 : X" simplifies to "X == 0 ? 1 : X".
> 
> $ cat t.c
> unsigned foo(unsigned x) {
>  if (x == 0) x++;
>  return x;
> }
> 
> $ clang -O3 t.c
> _foo:
> 	cmpl	$1, %edi
> 	movl	%edi, %eax
> 	adcl	$0, %eax
> 	ret

That's very nice.  I guess I was assuming that we'd canonicalize that into:

define i32 @bar(i32 %x) nounwind readnone ssp {
entry:
  %cmp = icmp eq i32 %x, 0
  %inc.x = select i1 %cmp, i32 1, i32 %x
  ret i32 %inc.x
}

which we don't.  This isels to:

_bar:                                   ## @bar
## BB#0:                                ## %entry
	testl	%edi, %edi
	movl	$1, %eax
	cmovnel	%edi, %eax
	ret

Which isn't too bad, but isn't as nice as the adc sequence because it uses an extra register :)

-Chris