[llvm-commits] [llvm] r122107 - in /llvm/trunk/lib/CodeGen: RegAllocBase.h RegAllocBasic.cpp RegAllocGreedy.cpp

[Jakob Stoklund Olesen]

Author: stoklund
Date: Fri Dec 17 17:16:35 2010
New Revision: 122107

URL: http://llvm.org/viewvc/llvm-project?rev=122107&view=rev
Log:
Make the -verify-regalloc command line option available to base classes as
RegAllocBase::VerifyEnabled.

Run the machine code verifier in a few interesting places during RegAllocGreedy.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocBase.h
    llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocBase.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBase.h?rev=122107&r1=122106&r2=122107&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBase.h (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBase.h Fri Dec 17 17:16:35 2010
@@ -156,6 +156,10 @@
   // Use this group name for NamedRegionTimer.
   static const char *TimerGroupName;
 
+public:
+  /// VerifyEnabled - True when -verify-regalloc is given.
+  static bool VerifyEnabled;
+
 private:
   void seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> >&);
 

Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=122107&r1=122106&r2=122107&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Fri Dec 17 17:16:35 2010
@@ -53,11 +53,12 @@
 
 // Temporary verification option until we can put verification inside
 // MachineVerifier.
-static cl::opt<bool>
-VerifyRegAlloc("verify-regalloc",
-               cl::desc("Verify live intervals before renaming"));
+static cl::opt<bool, true>
+VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
+               cl::desc("Verify during register allocation"));
 
 const char *RegAllocBase::TimerGroupName = "Register Allocation";
+bool RegAllocBase::VerifyEnabled = false;
 
 namespace {
 /// RABasic provides a minimal implementation of the basic register allocation
@@ -475,7 +476,7 @@
   // make the rewriter a separate pass and override verifyAnalysis instead. When
   // that happens, verification naturally falls under VerifyMachineCode.
 #ifndef NDEBUG
-  if (VerifyRegAlloc) {
+  if (VerifyEnabled) {
     // Verify accuracy of LiveIntervals. The standard machine code verifier
     // ensures that each LiveIntervals covers all uses of the virtual reg.
 

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=122107&r1=122106&r2=122107&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Fri Dec 17 17:16:35 2010
@@ -328,6 +328,9 @@
   SplitEditor(*SA, *LIS, *VRM, *DomTree, LREdit)
     .splitAroundLoop(Loop->getLoop());
 
+  if (VerifyEnabled)
+    MF->verify(this);
+
   // We have new split regs, don't assign anything.
   return 0;
 }
@@ -400,6 +403,9 @@
                << ((Value*)mf.getFunction())->getName() << '\n');
 
   MF = &mf;
+  if (VerifyEnabled)
+    MF->verify(this);
+
   RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
   DomTree = &getAnalysis<MachineDominatorTree>();
   ReservedRegs = TRI->getReservedRegs(*MF);