[llvm-commits] [llvm] r121846 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Author: lattner
Date: Tue Dec 14 23:51:39 2010
New Revision: 121846

URL: http://llvm.org/viewvc/llvm-project?rev=121846&view=rev
Log:
when transforming a MULHS into a wider MUL, there is no need to SRA the
result, the top bits are truncated off anyway, just use SRL.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=121846&r1=121845&r2=121846&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Dec 14 23:51:39 2010
@@ -1940,7 +1940,7 @@
       N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
       N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
       N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
-      N1 = DAG.getNode(ISD::SRA, DL, NewVT, N1,
+      N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
                        DAG.getConstant(SimpleSize, getShiftAmountTy()));
       return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
     }