[llvm-commits] [llvm] r121830 - /llvm/trunk/test/MC/ARM/arm_instructions.s

[Kevin Enderby]

Author: enderby
Date: Tue Dec 14 19:24:36 2010
New Revision: 121830

URL: http://llvm.org/viewvc/llvm-project?rev=121830&view=rev
Log:
Add some more MC tests for ARM arithmetic instructions that update or don't
update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.

Modified:
    llvm/trunk/test/MC/ARM/arm_instructions.s

Modified: llvm/trunk/test/MC/ARM/arm_instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=121830&r1=121829&r2=121830&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/arm_instructions.s (original)
+++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Dec 14 19:24:36 2010
@@ -56,11 +56,62 @@
         stmda     r2!, {r1,r3-r6,sp}
         stmdb     r2!, {r1,r3-r6,sp}
 
-@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
-        and r1, r2, r3
-@ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
-        ands r1, r2, r3
-@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
-        eor r1, r2, r3
-@ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
-        eors r1, r2, r3
+@ CHECK: and	r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
+        and r1,r2,r3
+
+@ CHECK: ands	r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
+        ands r1,r2,r3
+
+@ CHECK: eor	r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
+        eor r1,r2,r3
+
+@ CHECK: eors	r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
+        eors r1,r2,r3
+
+@ CHECK: sub	r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
+        sub r1,r2,r3
+
+@ CHECK: subs	r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0]
+        subs r1,r2,r3
+
+@ CHECK: add	r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0]
+        add r1,r2,r3
+
+@ CHECK: adds	r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0]
+        adds r1,r2,r3
+
+@ CHECK: adc	r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0]
+        adc r1,r2,r3
+
+@ CHECK: sbc	r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe0]
+        sbc r1,r2,r3
+
+@ CHECK: orr	r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1]
+        orr r1,r2,r3
+
+@ CHECK: orrs	r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1]
+        orrs r1,r2,r3
+
+@ CHECK: bic	r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1]
+        bic r1,r2,r3
+
+@ CHECK: bics	r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1]
+        bics r1,r2,r3
+
+@ CHECK: mov	r1, r2 @ encoding: [0x02,0x10,0xa0,0xe1]
+        mov r1,r2
+
+@ CHECK: mvn	r1, r2 @ encoding: [0x02,0x10,0xe0,0xe1]
+        mvn r1,r2
+
+@ CHECK: mvns	r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
+        mvns r1,r2
+
+@ CHECK: rsb	r1, r2, r3 @ encoding: [0x03,0x10,0x62,0xe0]
+        rsb r1,r2,r3
+
+@ CHECK: rsc	r1, r2, r3 @ encoding: [0x03,0x10,0xe2,0xe0]
+        rsc r1,r2,r3
+
+@ CHECK: mlas	r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0]
+        mlas r1,r2,r3,r4