[llvm-commits] [llvm] r121736 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

[Jakob Stoklund Olesen]

Author: stoklund
Date: Mon Dec 13 18:37:44 2010
New Revision: 121736

URL: http://llvm.org/viewvc/llvm-project?rev=121736&view=rev
Log:
Add stub for RAGreedy::trySplit.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=121736&r1=121735&r2=121736&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Dec 13 18:37:44 2010
@@ -83,6 +83,9 @@
   bool checkUncachedInterference(LiveInterval &, unsigned);
   bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
   bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg);
+
+  unsigned trySplit(LiveInterval&, AllocationOrder&,
+                    SmallVectorImpl<LiveInterval*>&);
 };
 } // end anonymous namespace
 
@@ -222,6 +225,15 @@
   return reassignVReg(*Q.interferingVRegs()[0], PhysReg);
 }
 
+/// trySplit - Try to split VirtReg or one of its interferences, making it
+/// assignable.
+/// @return Physreg when VirtReg may be assigned and/or new SplitVRegs.
+unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
+                            SmallVectorImpl<LiveInterval*>&SplitVRegs) {
+  NamedRegionTimer T("Splitter", TimerGroupName, TimePassesIsEnabled);
+  return 0;
+}
+
 unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
                                 SmallVectorImpl<LiveInterval*> &SplitVRegs) {
   // Populate a list of physical register spill candidates.
@@ -266,6 +278,10 @@
   PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(),
                            ReassignCands.end());
 
+  unsigned PhysReg = trySplit(VirtReg, Order, SplitVRegs);
+  if (PhysReg || !SplitVRegs.empty())
+    return PhysReg;
+
   // Try to spill another interfering reg with less spill weight.
   NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
   //