[llvm-commits] [llvm] r121604 - in /llvm/trunk/lib/CodeGen: RegAllocBase.h RegAllocBasic.cpp RegAllocGreedy.cpp

[Jakob Stoklund Olesen]

Author: stoklund
Date: Fri Dec 10 18:19:56 2010
New Revision: 121604

URL: http://llvm.org/viewvc/llvm-project?rev=121604&view=rev
Log:
Add named timer groups for the different stages of register allocation.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocBase.h
    llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocBase.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBase.h?rev=121604&r1=121603&r2=121604&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBase.h (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBase.h Fri Dec 10 18:19:56 2010
@@ -153,6 +153,9 @@
   void verify();
 #endif
 
+  // Use this group name for NamedRegionTimer.
+  static const char *TimerGroupName;
+
 private:
   void seedLiveVirtRegs(std::priority_queue<std::pair<float, unsigned> >&);
 

Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=121604&r1=121603&r2=121604&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Fri Dec 10 18:19:56 2010
@@ -42,6 +42,7 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/Timer.h"
 
 #include <cstdlib>
 
@@ -56,6 +57,8 @@
 VerifyRegAlloc("verify-regalloc",
                cl::desc("Verify live intervals before renaming"));
 
+const char *RegAllocBase::TimerGroupName = "Register Allocation";
+
 namespace {
 
 class PhysicalRegisterDescription : public AbstractRegisterDescription {
@@ -204,6 +207,7 @@
 }
 
 void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
+  NamedRegionTimer T("Initialize", TimerGroupName, TimePassesIsEnabled);
   TRI = &vrm.getTargetRegInfo();
   MRI = &vrm.getRegInfo();
   VRM = &vrm;
@@ -364,6 +368,7 @@
 
 // Add newly allocated physical registers to the MBB live in sets.
 void RegAllocBase::addMBBLiveIns(MachineFunction *MF) {
+  NamedRegionTimer T("MBB Live Ins", TimerGroupName, TimePassesIsEnabled);
   typedef SmallVector<MachineBasicBlock*, 8> MBBVec;
   MBBVec liveInMBBs;
   MachineBasicBlock &entryMBB = *MF->begin();

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=121604&r1=121603&r2=121604&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Fri Dec 10 18:19:56 2010
@@ -35,6 +35,7 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Support/Timer.h"
 
 using namespace llvm;
 
@@ -58,7 +59,7 @@
 
   /// Return the pass name.
   virtual const char* getPassName() const {
-    return "Basic Register Allocator";
+    return "Greedy Register Allocator";
   }
 
   /// RAGreedy analysis usage.
@@ -254,17 +255,19 @@
   // Try to reassign interfering physical register. Priority among
   // PhysRegSpillCands does not matter yet, because the reassigned virtual
   // registers will still be assigned to physical registers.
-  for (SmallVectorImpl<unsigned>::iterator PhysRegI = ReassignCands.begin(),
-         PhysRegE = ReassignCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
-    if (reassignInterferences(VirtReg, *PhysRegI))
-      // Reassignment successfull. The caller may allocate now to this PhysReg.
-      return *PhysRegI;
+  {
+    NamedRegionTimer T("Reassign", TimerGroupName, TimePassesIsEnabled);
+    for (SmallVectorImpl<unsigned>::iterator PhysRegI = ReassignCands.begin(),
+          PhysRegE = ReassignCands.end(); PhysRegI != PhysRegE; ++PhysRegI)
+      if (reassignInterferences(VirtReg, *PhysRegI))
+        // Reassignment successfull. Allocate now to this PhysReg.
+        return *PhysRegI;
   }
-
   PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(),
                            ReassignCands.end());
 
   // Try to spill another interfering reg with less spill weight.
+  NamedRegionTimer T("Spiller", TimerGroupName, TimePassesIsEnabled);
   //
   // FIXME: do this in two steps: (1) check for unspillable interferences while
   // accumulating spill weight; (2) spill the interferences with lowest
@@ -305,8 +308,11 @@
   addMBBLiveIns(MF);
 
   // Run rewriter
-  std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
-  rewriter->runOnMachineFunction(*MF, *VRM, LIS);
+  {
+    NamedRegionTimer T("Rewriter", TimerGroupName, TimePassesIsEnabled);
+    std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
+    rewriter->runOnMachineFunction(*MF, *VRM, LIS);
+  }
 
   // The pass output is in VirtRegMap. Release all the transient data.
   releaseMemory();