[llvm-commits] [llvm] r121358 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrInfo.td test/CodeGen/X86/tlv-1.ll

[Eric Christopher]

Author: echristo
Date: Thu Dec  9 00:25:53 2010
New Revision: 121358

URL: http://llvm.org/viewvc/llvm-project?rev=121358&view=rev
Log:
Rewrite the darwin tlv support to use a chain and return to copying
the output to the correct register. Fixes a hidden problem uncovered
by the last patch where we'd try to DAG combine our MVT::Other node
oddly.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.td
    llvm/trunk/test/CodeGen/X86/tlv-1.ll

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=121358&r1=121357&r2=121358&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Dec  9 00:25:53 2010
@@ -6181,7 +6181,7 @@
       OpFlag = X86II::MO_TLVP;
     DebugLoc DL = Op.getDebugLoc();
     SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
-                                                getPointerTy(),
+                                                GA->getValueType(0),
                                                 GA->getOffset(), OpFlag);
     SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
 
@@ -6194,8 +6194,10 @@
 
     // Lowering the machine isd will make sure everything is in the right
     // location.
-    SDValue Args[] = { Offset };
-    SDValue RetVal = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
+    SDValue Chain = DAG.getEntryNode();
+    SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
+    SDValue Args[] = { Chain, Offset };
+    Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
 
     // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
     MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
@@ -6203,7 +6205,8 @@
     
     // And our return value (tls address) is in the standard call return value
     // location.
-    return RetVal;
+    unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
+    return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
   }
 
   assert(false &&

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=121358&r1=121357&r2=121358&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Dec  9 00:25:53 2010
@@ -84,7 +84,7 @@
 
 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
-def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
+def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
@@ -212,7 +212,7 @@
                           [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
 
 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
-                        []>;
+                        [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
 //===----------------------------------------------------------------------===//
 // X86 Operand Definitions.

Modified: llvm/trunk/test/CodeGen/X86/tlv-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tlv-1.ll?rev=121358&r1=121357&r2=121358&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tlv-1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tlv-1.ll Thu Dec  9 00:25:53 2010
@@ -1,5 +1,21 @@
 ; RUN: llc < %s -mtriple x86_64-apple-darwin | FileCheck %s
 
+%struct.A = type { [48 x i8], i32, i32, i32 }
+
+ at c = external thread_local global %struct.A, align 4
+
+define void @main() nounwind ssp {
+entry:
+  call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds (%struct.A* @c, i32 0, i32 0, i32 0), i8 0, i64 60, i32 1, i1 false)
+  unreachable  
+  ; CHECK: movq    _c at TLVP(%rip), %rdi
+  ; CHECK-NEXT: callq   *(%rdi)
+  ; CHECK-NEXT: movl    $0, 56(%rax)
+  ; CHECK-NEXT: movq    $0, 48(%rax)
+}
+
+declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
+
 @a = thread_local global i32 0                    ; <i32*> [#uses=0]
 @b = thread_local global i32 0                    ; <i32*> [#uses=0]