[llvm-commits] [llvm] r121345 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

[Jim Grosbach]

Author: grosbach
Date: Wed Dec  8 19:21:27 2010
New Revision: 121345

URL: http://llvm.org/viewvc/llvm-project?rev=121345&view=rev
Log:
The add/sub SP instructions are really pseudos. The assembler should ignore
them.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=121345&r1=121344&r2=121345&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Dec  8 19:21:27 2010
@@ -1160,6 +1160,7 @@
 // add/sub instructions. In thumb1 we need them since they have dedicated
 // encodings. At the least, they should be pseudo instructions.
 // ADD r, sp, {so_imm|i12}
+let isCodeGenOnly = 1 in {
 def t2ADDrSPi   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
                         IIC_iALUi, "add", ".w\t$Rd, $Rn, $imm", []> {
   let Inst{31-27} = 0b11110;
@@ -1209,6 +1210,7 @@
   let Inst{19-16} = 0b1101; // Rn = sp
   let Inst{15} = 0;
 }
+} // end isCodeGenOnly = 1
 
 // Signed and unsigned division on v7-M
 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,