[llvm-commits] [llvm] r121312 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMInstrInfo.td test/CodeGen/ARM/2010-12-08-tpsoft.ll
Jason W Kim
jason.w.kim.2009 at gmail.com
Wed Dec 8 15:14:44 PST 2010
Author: jasonwkim
Date: Wed Dec 8 17:14:44 2010
New Revision: 121312
URL: http://llvm.org/viewvc/llvm-project?rev=121312&view=rev
Log:
ARM/MC/ELF TPsoft is now a proper pseudo inst.
Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)
Also added support for ELF::R_ARM_TLS_IE32
Added:
llvm/trunk/test/CodeGen/ARM/2010-12-08-tpsoft.ll
Modified:
llvm/trunk/lib/MC/ELFObjectWriter.cpp
llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=121312&r1=121311&r2=121312&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 8 17:14:44 2010
@@ -1533,6 +1533,7 @@
MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ?
MCSymbolRefExpr::VK_None : Target.getSymA()->getKind();
+ unsigned Type = 0;
if (IsPCRel) {
switch (Modifier) {
default: assert(0 && "Unimplemented Modifier");
@@ -1540,11 +1541,17 @@
}
switch ((unsigned)Fixup.getKind()) {
default: assert(0 && "Unimplemented");
- case ARM::fixup_arm_branch: return ELF::R_ARM_CALL; break;
+ case ARM::fixup_arm_branch: Type = ELF::R_ARM_CALL; break;
}
} else {
switch ((unsigned)Fixup.getKind()) {
default: llvm_unreachable("invalid fixup kind!");
+ case FK_Data_4:
+ switch (Modifier) {
+ default: llvm_unreachable("Unsupported Modifier");
+ case MCSymbolRefExpr::VK_ARM_GOTTPOFF:
+ Type = ELF::R_ARM_TLS_IE32;
+ } break;
case ARM::fixup_arm_ldst_pcrel_12:
case ARM::fixup_arm_pcrel_10:
case ARM::fixup_arm_adr_pcrel_12:
@@ -1553,17 +1560,18 @@
case ARM::fixup_arm_thumb_cp:
assert(0 && "Unimplemented"); break;
case ARM::fixup_arm_branch:
- return ELF::R_ARM_CALL; break;
+ Type = ELF::R_ARM_CALL; break;
case ARM::fixup_arm_movt_hi16:
- return ELF::R_ARM_MOVT_ABS; break;
+ Type = ELF::R_ARM_MOVT_ABS; break;
case ARM::fixup_arm_movw_lo16:
- return ELF::R_ARM_MOVW_ABS_NC; break;
+ Type = ELF::R_ARM_MOVW_ABS_NC; break;
}
}
if (RelocNeedsGOT(Modifier))
NeedsGOT = true;
- return -1;
+
+ return Type;
}
//===- MBlazeELFObjectWriter -------------------------------------------===//
Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=121312&r1=121311&r2=121312&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Wed Dec 8 17:14:44 2010
@@ -699,6 +699,21 @@
MI.eraseFromParent();
break;
}
+ case ARM::TPsoft: {
+ unsigned PredReg = 0;
+ ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg);
+ MachineInstrBuilder MIB =
+ BuildMI(MBB, MBBI, MI.getDebugLoc(),
+ TII->get(ARM::BL))
+ .addExternalSymbol("__aeabi_read_tp", 0);
+
+ (*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
+ TransferImpOps(MI, MIB, MIB);
+ MI.eraseFromParent();
+
+ //assert(0 && "HELP!");
+ }; break;
+
case ARM::t2LDRHpci:
case ARM::t2LDRBpci:
case ARM::t2LDRSHpci:
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=121312&r1=121311&r2=121312&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Dec 8 17:14:44 2010
@@ -3249,12 +3249,11 @@
//
// __aeabi_read_tp preserves the registers r1-r3.
-// FIXME: This needs to be a pseudo of some sort so that we can get the
-// encoding right, complete with fixup for the aeabi_read_tp function.
+// This is a pseudo inst so that we can get the encoding right,
+// complete with fixup for the aeabi_read_tp function.
let isCall = 1,
Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
- def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
- "bl\t__aeabi_read_tp",
+ def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
[(set R0, ARMthread_pointer)]>;
}
Added: llvm/trunk/test/CodeGen/ARM/2010-12-08-tpsoft.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-12-08-tpsoft.ll?rev=121312&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-12-08-tpsoft.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2010-12-08-tpsoft.ll Wed Dec 8 17:14:44 2010
@@ -0,0 +1,52 @@
+; RUN: llc %s -mtriple=armv7-linux-gnueabi -o - | \
+; RUN: FileCheck -check-prefix=ELFASM %s
+; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \
+; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=ELFOBJ %s
+
+;; Make sure that bl __aeabi_read_tp is materiazlied and fixed up correctly
+;; in the obj case.
+
+ at i = external thread_local global i32
+ at a = external global i8
+ at b = external global [10 x i8]
+
+define arm_aapcs_vfpcc i32 @main() nounwind {
+entry:
+ %0 = load i32* @i, align 4
+ switch i32 %0, label %bb2 [
+ i32 12, label %bb
+ i32 13, label %bb1
+ ]
+
+bb: ; preds = %entry
+ %1 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind
+ ret i32 %1
+; ELFASM: bl __aeabi_read_tp
+
+
+; ELFOBJ: '.text'
+; ELFOBJ-NEXT: 'sh_type'
+; ELFOBJ-NEXT: 'sh_flags'
+; ELFOBJ-NEXT: 'sh_addr'
+; ELFOBJ-NEXT: 'sh_offset'
+; ELFOBJ-NEXT: 'sh_size'
+; ELFOBJ-NEXT: 'sh_link'
+; ELFOBJ-NEXT: 'sh_info'
+; ELFOBJ-NEXT: 'sh_addralign'
+; ELFOBJ-NEXT: 'sh_entsize'
+;;; BL __aeabi_read_tp is ---+
+;;; V
+; ELFOBJ-NEXT: 00482de9 3c009fe5 00109fe7 feffffeb
+
+
+bb1: ; preds = %entry
+ %2 = tail call arm_aapcs_vfpcc i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind
+ ret i32 %2
+
+bb2: ; preds = %entry
+ ret i32 -1
+}
+
+declare arm_aapcs_vfpcc i32 @foo(i8*)
+
+declare arm_aapcs_vfpcc i32 @bar(i32*)
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