[llvm-commits] [llvm] r121310 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

[Jim Grosbach]

Author: grosbach
Date: Wed Dec  8 17:12:09 2010
New Revision: 121310

URL: http://llvm.org/viewvc/llvm-project?rev=121310&view=rev
Log:
Add operand encoding for Thumb2 subw SP + imm. rdar://8745434

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=121310&r1=121309&r2=121310&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Dec  8 17:12:09 2010
@@ -1195,12 +1195,16 @@
 }
 def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$sp, imm0_4095:$imm),
                        IIC_iALUi, "subw", "\t$Rd, $sp, $imm", []> {
+  bits<4> Rd;
+  bits<12> imm;
   let Inst{31-27} = 0b11110;
-  let Inst{25} = 1;
-  let Inst{24-21} = 0b0101;
-  let Inst{20} = 0; // The S bit.
+  let Inst{26} = imm{11};
+  let Inst{25-20} = 0b101010;
   let Inst{19-16} = 0b1101; // Rn = sp
   let Inst{15} = 0;
+  let Inst{14-12} = imm{10-8};
+  let Inst{11-8} = Rd;
+  let Inst{7-0} = imm{7-0};
 }
 
 // SUB r, sp, so_reg