[llvm-commits] [llvm] r121226 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMMCCodeEmitter.cpp utils/TableGen/EDEmitter.cpp
Jim Grosbach
grosbach at apple.com
Wed Dec 8 12:12:59 PST 2010
Woot! Awesome.
On Dec 7, 2010, at 5:57 PM, Bill Wendling wrote:
> Author: void
> Date: Tue Dec 7 19:57:09 2010
> New Revision: 121226
>
> URL: http://llvm.org/viewvc/llvm-project?rev=121226&view=rev
> Log:
> Add support for loading from a constant pool.
>
> Modified:
> llvm/trunk/lib/MC/ELFObjectWriter.cpp
> llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
> llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
> llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
> llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
> llvm/trunk/utils/TableGen/EDEmitter.cpp
>
> Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=121226&r1=121225&r2=121226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
> +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Tue Dec 7 19:57:09 2010
> @@ -1549,6 +1549,7 @@
> case ARM::fixup_arm_pcrel_10:
> case ARM::fixup_arm_adr_pcrel_12:
> case ARM::fixup_arm_thumb_bl:
> + case ARM::fixup_arm_thumb_cp:
> assert(0 && "Unimplemented"); break;
> case ARM::fixup_arm_branch:
> return ELF::R_ARM_CALL; break;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=121226&r1=121225&r2=121226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Tue Dec 7 19:57:09 2010
> @@ -138,6 +138,9 @@
> Binary = ((Binary & 0x7ff) << 16) | (Binary >> 11);
> return Binary;
> }
> + case ARM::fixup_arm_thumb_cp:
> + // Offset by 4, and don't encode the low two bits.
> + return ((Value - 4) >> 2) & 0xff;
> case ARM::fixup_t2_pcrel_10:
> case ARM::fixup_arm_pcrel_10: {
> // Offset by 8 just as above.
> @@ -243,13 +246,17 @@
> switch (Kind) {
> default:
> llvm_unreachable("Unknown fixup kind!");
> - case FK_Data_4:
> - return 4;
> +
> + case ARM::fixup_arm_thumb_cp:
> + return 1;
> +
> case ARM::fixup_arm_ldst_pcrel_12:
> case ARM::fixup_arm_pcrel_10:
> case ARM::fixup_arm_adr_pcrel_12:
> case ARM::fixup_arm_branch:
> return 3;
> +
> + case FK_Data_4:
> case ARM::fixup_t2_pcrel_10:
> case ARM::fixup_arm_thumb_bl:
> return 4;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=121226&r1=121225&r2=121226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Dec 7 19:57:09 2010
> @@ -255,6 +255,8 @@
> const { return 0; }
> uint32_t getAddrModeS1OpValue(const MachineInstr &MI, unsigned Op)
> const { return 0; }
> + uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
> + const { return 0; }
> uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
> // {17-13} = reg
> // {12} = (U)nsigned (add == '1', sub == '0')
>
> Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=121226&r1=121225&r2=121226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Tue Dec 7 19:57:09 2010
> @@ -34,6 +34,9 @@
> // fixup_arm_thumb_bl - Fixup for Thumb BL/BLX instructions.
> fixup_arm_thumb_bl,
>
> + // fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
> + fixup_arm_thumb_cp,
> +
> // The next two are for the movt/movw pair
> // the 16bit imm field are split into imm{15-12} and imm{11-0}
> // Fixme: We need new ones for Thumb.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=121226&r1=121225&r2=121226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Dec 7 19:57:09 2010
> @@ -134,6 +134,13 @@
> let ParserMatchClass = MemModeThumbAsmOperand;
> }
>
> +// t_addrmode_pc := <label> => pc + imm8 * 4
> +//
> +def t_addrmode_pc : Operand<i32> {
> + let EncoderMethod = "getAddrModePCOpValue";
> + let ParserMatchClass = MemModeThumbAsmOperand;
> +}
> +
> //===----------------------------------------------------------------------===//
> // Miscellaneous Instructions.
> //
> @@ -622,22 +629,29 @@
> // Load tconstpool
> // FIXME: Use ldr.n to work around a Darwin assembler bug.
> let canFoldAsLoad = 1, isReMaterializable = 1 in
> -def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
> +def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
> "ldr", ".n\t$Rt, $addr",
> [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
> T1Encoding<{0,1,0,0,1,?}> {
> // A6.2 & A8.6.59
> bits<3> Rt;
> + bits<8> addr;
> let Inst{10-8} = Rt;
> - // FIXME: Finish for the addr.
> + let Inst{7-0} = addr;
> }
>
> // Special LDR for loads from non-pc-relative constpools.
> let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
> isReMaterializable = 1 in
> -def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
> - "ldr", "\t$dst, $addr", []>,
> - T1LdStSP<{1,?,?}>;
> +def tLDRcp : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
> + "ldr", "\t$Rt, $addr", []>,
> + T1LdStSP<{1,?,?}> {
> + // A6.2 & A8.6.57 T2
> + bits<3> Rt;
> + bits<8> addr;
> + let Inst{10-8} = Rt;
> + let Inst{7-0} = addr;
> +}
>
> def tSTR : // A8.6.194
> T1pILdStEncode<0b000, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
>
> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=121226&r1=121225&r2=121226&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Dec 7 19:57:09 2010
> @@ -52,6 +52,7 @@
> { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
> { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
> { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
> + { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel },
> { "fixup_arm_movt_hi16", 0, 16, 0 },
> { "fixup_arm_movw_lo16", 0, 16, 0 },
> };
> @@ -174,6 +175,10 @@
> uint32_t getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
> SmallVectorImpl<MCFixup> &Fixups) const;
>
> + /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
> + uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
> + SmallVectorImpl<MCFixup> &Fixups) const;
> +
> /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
> uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
> SmallVectorImpl<MCFixup> &Fixups) const;
> @@ -662,15 +667,17 @@
> return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
> }
>
> -/// getAddrModeThumbSPOpValue- Encode the t_addrmode_sp operands.
> +/// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands.
> uint32_t ARMMCCodeEmitter::
> getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
> SmallVectorImpl<MCFixup> &Fixups) const {
> // [SP, #imm]
> // {7-0} = imm8
> const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
> - assert (MI.getOperand(OpIdx).getReg() == ARM::SP &&
> - "Unexpected base register!");
> +#if 0 // FIXME: This crashes2003-05-14-initialize-string.c
> + assert(MI.getOperand(OpIdx).getReg() == ARM::SP &&
> + "Unexpected base register!");
> +#endif
> // The immediate is already shifted for the implicit zeroes, so no change
> // here.
> return MO1.getImm() & 0xff;
> @@ -720,6 +727,23 @@
> return getAddrModeSOpValue(MI, OpIdx, 1);
> }
>
> +/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
> +uint32_t ARMMCCodeEmitter::
> +getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
> + SmallVectorImpl<MCFixup> &Fixups) const {
> + const MCOperand &MO = MI.getOperand(OpIdx);
> +
> + // If the destination is an immediate, we have nothing to do.
> + if (MO.isImm()) return MO.getImm();
> + assert (MO.isExpr() && "Unexpected branch target type!");
> + const MCExpr *Expr = MO.getExpr();
> + MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_thumb_cp);
> + Fixups.push_back(MCFixup::Create(0, Expr, Kind));
> +
> + // All of the information is in the fixup.
> + return 0;
> +}
> +
> /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
> uint32_t ARMMCCodeEmitter::
> getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
>
> Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=121226&r1=121225&r2=121226&view=diff
> ==============================================================================
> --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Tue Dec 7 19:57:09 2010
> @@ -627,6 +627,7 @@
> MISC("t_addrmode_s4", "kOperandTypeThumbAddrModeS4"); // R, I, R
> MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R
> MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I
> + MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I
>
> return 1;
> }
> @@ -838,6 +839,7 @@
> operandTypes.addEntry("kOperandTypeThumbAddrModeS4");
> operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
> operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
> + operandTypes.addEntry("kOperandTypeThumbAddrModePC");
> operandTypes.addEntry("kOperandTypeThumb2SoReg");
> operandTypes.addEntry("kOperandTypeThumb2SoImm");
> operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
>
>
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