[llvm-commits] [llvm] r121021 - in /llvm/trunk/lib/Target/ARM: ARMExpandPseudoInsts.cpp ARMInstrThumb2.td

[Jim Grosbach]

Hi Owen,

Clang is complaining about "DstIsDead" being unused (which is correct). Since there's no PICADD instruction here, it looks like that local var can just be deleted?

-Jim

On Dec 6, 2010, at 10:35 AM, Owen Anderson wrote:

> Author: resistor
> Date: Mon Dec  6 12:35:51 2010
> New Revision: 121021
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=121021&view=rev
> Log:
> Improve handling of Thumb2 PC-relative loads by converting LDRpci (and friends) to Pseudos.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
>    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=121021&r1=121020&r2=121021&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Dec  6 12:35:51 2010
> @@ -699,6 +699,36 @@
>       MI.eraseFromParent();
>       break;
>     }
> +    case ARM::t2LDRHpci:
> +    case ARM::t2LDRBpci:
> +    case ARM::t2LDRSHpci:
> +    case ARM::t2LDRSBpci:
> +    case ARM::t2LDRpci: {
> +      unsigned NewLdOpc;
> +      if (Opcode == ARM::t2LDRpci)
> +        NewLdOpc = ARM::t2LDRi12;
> +      else if (Opcode == ARM::t2LDRHpci)
> +        NewLdOpc = ARM::t2LDRHi12;
> +      else if (Opcode == ARM::t2LDRBpci)
> +        NewLdOpc = ARM::t2LDRBi12;
> +      else if (Opcode == ARM::t2LDRSHpci)
> +        NewLdOpc = ARM::t2LDRSHi12;
> +      else if (Opcode == ARM::t2LDRSBpci)
> +        NewLdOpc = ARM::t2LDRSBi12;
> +      else
> +        llvm_unreachable("Not a known opcode?");
> +            
> +      unsigned DstReg = MI.getOperand(0).getReg();
> +      bool DstIsDead = MI.getOperand(0).isDead();
> +      MachineInstrBuilder MIB =
> +        BuildMI(MBB, MBBI, MI.getDebugLoc(),
> +                               TII->get(NewLdOpc), DstReg)
> +                       .addOperand(MI.getOperand(1));
> +      (*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
> +      TransferImpOps(MI, MIB, MIB);
> +      MI.eraseFromParent();
> +      break;
> +    }
>     case ARM::tLDRpci_pic:
>     case ARM::t2LDRpci_pic: {
>       unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
> @@ -706,9 +736,9 @@
>       unsigned DstReg = MI.getOperand(0).getReg();
>       bool DstIsDead = MI.getOperand(0).isDead();
>       MachineInstrBuilder MIB1 =
> -        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
> +        BuildMI(MBB, MBBI, MI.getDebugLoc(),
>                                TII->get(NewLdOpc), DstReg)
> -                       .addOperand(MI.getOperand(1)));
> +                       .addOperand(MI.getOperand(1));
>       (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
>       MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
>                                          TII->get(ARM::tPICADD))
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=121021&r1=121020&r2=121021&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Dec  6 12:35:51 2010
> @@ -888,24 +888,8 @@
>     let Inst{5-4}   = addr{1-0}; // imm
>   }
> 
> -  // FIXME: Is the pci variant actually needed?
> -  def pci : T2Ipc <(outs GPR:$Rt), (ins i32imm:$addr), iii,
> -                   opc, ".w\t$Rt, $addr",
> -                   [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> {
> -    let isReMaterializable = 1;
> -    let Inst{31-27} = 0b11111;
> -    let Inst{26-25} = 0b00;
> -    let Inst{24} = signed;
> -    let Inst{23} = ?; // add = (U == '1')
> -    let Inst{22-21} = opcod;
> -    let Inst{20} = 1; // load
> -    let Inst{19-16} = 0b1111; // Rn
> -
> -    bits<4> Rt;
> -    bits<12> addr;
> -    let Inst{15-12} = Rt{3-0};
> -    let Inst{11-0}  = addr{11-0};
> -  }
> +  def pci : tPseudoInst<(outs GPR:$Rt), (ins i32imm:$addr), Size4Bytes, iis,
> +                      [(set GPR:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]>;
> }
> 
> /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits