[llvm-commits] [llvm] r120932 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/select.ll

[Evan Cheng]

On Dec 5, 2010, at 4:47 PM, Chris Lattner wrote:

> On Dec 5, 2010, at 4:36 PM, Chris Lattner wrote:
> On Dec 5, 2010, at 3:32 PM, Evan Cheng wrote:
>>>> but this also helps if the other value is an imm or load, because those can be folded into orq but not into cmov.
>>> 
>>> That may be true. I'd still call this optimization suspect. A couple of cycles of latencies means very little for modern x86. Instruction throughput is probably just as important and the extra instruction here may actually be an pessimisation.
>>> 
>>> Both gcc and icc just generates something like this. What are we missing? It doesn't seem like they are concerned with overflow?
>>>      salq    $2, %rdi
>>>      jmp     __Znam
>> 
>> Right, they don't handle the integer overflow case.  In this particular example, what we really want is a way to say that the select is heavily biased, so that we get a jump instead of cmov (or cmov equivalent).  We really want:
>> 
>> mulq <reg>
>> jo Lfoo
>> jmp __Znam
>> Lfoo:
>> mov rdi, -1
>> jmp __Znam
> 
> Along these lines, I wonder if it would be enough to just mark IR select/condbr instructions with an instruction MDNode like !highlybiased (optionally with a direction).  This could be preserved down to codegen level and used for expansion there.  This would also be a straight-forward way to model __builtin_expect.

Do we want to make it a more generic MDNode so we can use it to encode branch probability?

Evan

> 
> -Chris