[llvm-commits] [llvm] r120932 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/select.ll

[Evan Cheng]

On Dec 4, 2010, at 6:00 PM, Chris Lattner wrote:

> Author: lattner
> Date: Sat Dec  4 20:00:51 2010
> New Revision: 120932
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=120932&view=rev
> Log:
> generalize the previous check to handle -1 on either side of the 
> select, inserting a not to compensate.  Add a missing isZero check
> that I lost somehow.
> 
> This improves codegen of:
> 
> void *func(long count) {
>      return new int[count];
> }
> 
> from:
> 
> __Z4funcl:                              ## @_Z4funcl
> 	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
> 	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
> 	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
> 	testq	%rdx, %rdx              ## encoding: [0x48,0x85,0xd2]
> 	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
> 	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
> 	jmp	__Znam                  ## TAILCALL
>                                        ## encoding: [0xeb,A]
> 
> to:
> 
> __Z4funcl:                              ## @_Z4funcl
> 	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
> 	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
> 	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
> 	cmpq	$1, %rdx                ## encoding: [0x48,0x83,0xfa,0x01]
> 	sbbq	%rdi, %rdi              ## encoding: [0x48,0x19,0xff]
> 	notq	%rdi                    ## encoding: [0x48,0xf7,0xd7]
> 	orq	%rax, %rdi              ## encoding: [0x48,0x09,0xc7]
> 	jmp	__Znam                  ## TAILCALL
>                                        ## encoding: [0xeb,A]

Why is this an improvement?

Evan

> 
> 
> Modified:
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>    llvm/trunk/test/CodeGen/X86/select.ll
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=120932&r1=120931&r2=120932&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Dec  4 20:00:51 2010
> @@ -7213,6 +7213,11 @@
>   return C && C->isNullValue();
> }
> 
> +static bool isAllOnes(SDValue V) {
> +  ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
> +  return C && C->isAllOnesValue();
> +}
> +
> SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
>   bool addTest = true;
>   SDValue Cond  = Op.getOperand(0);
> @@ -7228,26 +7233,31 @@
>   }
> 
>   // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
> +  // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
>   // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
> +  // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
>   if (Cond.getOpcode() == X86ISD::SETCC &&
> -      Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
> +      Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
> +      isZero(Cond.getOperand(1).getOperand(1))) {
>     SDValue Cmp = Cond.getOperand(1);
> 
>     unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
> 
> -    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
> -    ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
> -    if ((N1C && N1C->isAllOnesValue() && CondCode == X86::COND_E) ||
> -        (N2C && N2C->isAllOnesValue() && CondCode == X86::COND_NE)) {
> -      SDValue Y = CondCode == X86::COND_NE ? Op1 : Op2;
> +    if ((isAllOnes(Op1) || isAllOnes(Op2)) && 
> +        (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
> +      SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
> 
>       SDValue CmpOp0 = Cmp.getOperand(0);
>       Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
>                         CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
> 
> -      SDValue Res = 
> +      SDValue Res =   // Res = 0 or -1.
>         DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
>                     DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
> +      
> +      if (isAllOnes(Op1) != (CondCode == X86::COND_E))
> +        Res = DAG.getNOT(DL, Res, Res.getValueType());
> +      
>       ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
>       if (N2C == 0 || !N2C->isNullValue())
>         Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
> 
> Modified: llvm/trunk/test/CodeGen/X86/select.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/select.ll?rev=120932&r1=120931&r2=120932&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/select.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/select.ll Sat Dec  4 20:00:51 2010
> @@ -153,5 +153,29 @@
> 
> 
> 
> +define i64 @test11(i64 %x, i64 %y) nounwind readnone ssp noredzone {
> +  %cmp = icmp eq i64 %x, 0
> +  %cond = select i1 %cmp, i64 %y, i64 -1
> +  ret i64 %cond
> +; CHECK: test11:
> +; CHECK: cmpq	$1, %rdi
> +; CHECK: sbbq	%rax, %rax
> +; CHECK: notq %rax
> +; CHECK: orq	%rsi, %rax
> +; CHECK: ret
> +}
> +
> +define i64 @test11a(i64 %x, i64 %y) nounwind readnone ssp noredzone {
> +  %cmp = icmp ne i64 %x, 0
> +  %cond = select i1 %cmp, i64 -1, i64 %y
> +  ret i64 %cond
> +; CHECK: test11a:
> +; CHECK: cmpq	$1, %rdi
> +; CHECK: sbbq	%rax, %rax
> +; CHECK: notq %rax
> +; CHECK: orq	%rsi, %rax
> +; CHECK: ret
> +}
> +
> 
> 
> 
> 
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