[llvm-commits] [llvm] r120782 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

[Bill Wendling]

Author: void
Date: Thu Dec  2 20:02:58 2010
New Revision: 120782

URL: http://llvm.org/viewvc/llvm-project?rev=120782&view=rev
Log:
Don't overwrite the opcode passed into the T1Special pattern.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=120782&r1=120781&r2=120782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Dec  2 20:02:58 2010
@@ -1010,8 +1010,8 @@
   // A8.6.97
   bits<4> Rd;
   bits<4> Rm;
-  let Inst{7}   = Rd{3};
-  let Inst{6-3} = Rm;
+  // Bits {7-6} are encoded by the T1Special value.
+  let Inst{5-3} = Rm{2-0};
   let Inst{2-0} = Rd{2-0};
 }
 let Defs = [CPSR] in
@@ -1032,7 +1032,7 @@
   // A8.6.97
   bits<4> Rd;
   bits<4> Rm;
-  let Inst{7}   = Rd{3};
+  // Bit {7} is encoded by the T1Special value.
   let Inst{6-3} = Rm;
   let Inst{2-0} = Rd{2-0};
 }
@@ -1042,8 +1042,9 @@
   // A8.6.97
   bits<4> Rd;
   bits<4> Rm;
+  // Bit {6} is encoded by the T1Special value.
   let Inst{7}   = Rd{3};
-  let Inst{6-3} = Rm;
+  let Inst{5-3} = Rm{2-0};
   let Inst{2-0} = Rd{2-0};
 }
 def tMOVgpr2gpr  : T1I<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,