[llvm-commits] [llvm] r120766 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

[Bill Wendling]

Author: void
Date: Thu Dec  2 18:53:22 2010
New Revision: 120766

URL: http://llvm.org/viewvc/llvm-project?rev=120766&view=rev
Log:
The tLDR instruction wasn't encoded properly:

<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>

Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.

Modified:
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=120766&r1=120765&r2=120766&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Dec  2 18:53:22 2010
@@ -642,8 +642,12 @@
   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
   unsigned Rn = getARMRegisterNumbering(MO.getReg());
   unsigned Imm5 = (MO1.getImm() / Scale) & 0x1f;
-  unsigned Rm = getARMRegisterNumbering(MO2.getReg());
-  return (Rm << 3) | (Imm5 << 3) | Rn;
+
+  if (MO2.getReg() != 0)
+    // Is an immediate.
+    Imm5 = getARMRegisterNumbering(MO2.getReg());
+
+  return (Imm5 << 3) | Rn;
 }
 
 /// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands.