[llvm-commits] [llvm] r120635 - in /llvm/trunk/lib: MC/ELFObjectWriter.cpp MC/MachObjectWriter.cpp Target/ARM/ARMAsmBackend.cpp Target/ARM/ARMAsmPrinter.cpp Target/ARM/ARMFixupKinds.h Target/ARM/ARMInstrInfo.td Target/ARM/ARMMCCodeEmitter.cpp
Jim Grosbach
grosbach at apple.com
Wed Dec 1 16:28:45 PST 2010
Author: grosbach
Date: Wed Dec 1 18:28:45 2010
New Revision: 120635
URL: http://llvm.org/viewvc/llvm-project?rev=120635&view=rev
Log:
Add support for binary encoding of ARM 'adr' instructions referencing constant
pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291.
Modified:
llvm/trunk/lib/MC/ELFObjectWriter.cpp
llvm/trunk/lib/MC/MachObjectWriter.cpp
llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=120635&r1=120634&r2=120635&view=diff
==============================================================================
--- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Dec 1 18:28:45 2010
@@ -408,7 +408,7 @@
case FK_PCRel_1:
case FK_PCRel_2:
case FK_PCRel_4:
- case ARM::fixup_arm_pcrel_12:
+ case ARM::fixup_arm_ldst_pcrel_12:
case ARM::fixup_arm_pcrel_10:
case ARM::fixup_arm_branch:
return true;
@@ -1456,8 +1456,9 @@
} else {
switch ((unsigned)Fixup.getKind()) {
default: llvm_unreachable("invalid fixup kind!");
- case ARM::fixup_arm_pcrel_12:
+ case ARM::fixup_arm_ldst_pcrel_12:
case ARM::fixup_arm_pcrel_10:
+ case ARM::fixup_arm_adr_pcrel_12:
assert(0 && "Unimplemented"); break;
case ARM::fixup_arm_branch:
return ELF::R_ARM_CALL; break;
Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=120635&r1=120634&r2=120635&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Wed Dec 1 18:28:45 2010
@@ -31,7 +31,12 @@
// FIXME: this has been copied from (or to) X86AsmBackend.cpp
static unsigned getFixupKindLog2Size(unsigned Kind) {
switch (Kind) {
- default: llvm_unreachable("invalid fixup kind!");
+ // FIXME: Until ARM has it's own relocation stuff spun off, it comes
+ // through here and we don't want it to puke all over. Any reasonable
+ // values will only come when ARM relocation support gets added, at which
+ // point this will be X86 only again and the llvm_unreachable can be
+ // re-enabled.
+ default: return 0;// llvm_unreachable("invalid fixup kind!");
case FK_PCRel_1:
case FK_Data_1: return 0;
case FK_PCRel_2:
Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=120635&r1=120634&r2=120635&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Wed Dec 1 18:28:45 2010
@@ -7,8 +7,8 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/Target/TargetAsmBackend.h"
#include "ARM.h"
+#include "ARMAddressingModes.h"
#include "ARMFixupKinds.h"
#include "llvm/ADT/Twine.h"
#include "llvm/MC/MCAssembler.h"
@@ -21,6 +21,7 @@
#include "llvm/Support/ELF.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetAsmBackend.h"
#include "llvm/Target/TargetRegistry.h"
using namespace llvm;
@@ -67,7 +68,7 @@
case ARM::fixup_arm_movt_hi16:
case ARM::fixup_arm_movw_lo16:
return Value;
- case ARM::fixup_arm_pcrel_12: {
+ case ARM::fixup_arm_ldst_pcrel_12: {
bool isAdd = true;
// ARM PC-relative values are offset by 8.
Value -= 8;
@@ -79,6 +80,19 @@
Value |= isAdd << 23;
return Value;
}
+ case ARM::fixup_arm_adr_pcrel_12: {
+ // ARM PC-relative values are offset by 8.
+ Value -= 8;
+ unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
+ if ((int64_t)Value < 0) {
+ Value = -Value;
+ opc = 2; // 0b0010
+ }
+ assert(ARM_AM::getSOImmVal(Value) != -1 &&
+ "Out of range pc-relative fixup value!");
+ // Encode the immediate and shift the opcode into place.
+ return ARM_AM::getSOImmVal(Value) | (opc << 21);
+ }
case ARM::fixup_arm_branch:
// These values don't encode the low two bits since they're always zero.
// Offset by 8 just as above.
@@ -200,8 +214,9 @@
switch (Kind) {
default: llvm_unreachable("Unknown fixup kind!");
case FK_Data_4: return 4;
- case ARM::fixup_arm_pcrel_12: return 3;
+ case ARM::fixup_arm_ldst_pcrel_12: return 3;
case ARM::fixup_arm_pcrel_10: return 3;
+ case ARM::fixup_arm_adr_pcrel_12: return 3;
case ARM::fixup_arm_branch: return 3;
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=120635&r1=120634&r2=120635&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Dec 1 18:28:45 2010
@@ -726,13 +726,29 @@
}
return;
}
+ case ARM::LEApcrel: {
+ // FIXME: Need to also handle globals and externals
+ assert (MI->getOperand(1).isCPI());
+ unsigned LabelId = MI->getOperand(1).getIndex();
+ MCSymbol *Sym = GetCPISymbol(LabelId);
+ const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Sym, OutContext);
+ MCInst TmpInst;
+ TmpInst.setOpcode(ARM::ADR);
+ TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+ TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
+ // Add predicate operands.
+ TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+ TmpInst.addOperand(MCOperand::CreateReg(0));
+ OutStreamer.EmitInstruction(TmpInst);
+ return;
+ }
case ARM::LEApcrelJT: {
unsigned JTI = MI->getOperand(1).getIndex();
unsigned Id = MI->getOperand(2).getImm();
MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, Id);
const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(JTISymbol, OutContext);
MCInst TmpInst;
- TmpInst.setOpcode(ARM::ADRadd);
+ TmpInst.setOpcode(ARM::ADR);
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
// Add predicate operands.
Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=120635&r1=120634&r2=120635&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Wed Dec 1 18:28:45 2010
@@ -15,12 +15,16 @@
namespace llvm {
namespace ARM {
enum Fixups {
- // fixup_arm_pcrel_12 - 12-bit PC relative relocation for symbol addresses
- fixup_arm_pcrel_12 = FirstTargetFixupKind,
+ // fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol
+ // addresses
+ fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
// fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
// used in VFP and Thumb2 instructions where the lower 2 bits are not encoded
// (so it's encoded as an 8-bit immediate).
fixup_arm_pcrel_10,
+ // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
+ // instruction.
+ fixup_arm_adr_pcrel_12,
// fixup_arm_brnach - 24-bit PC relative relocation for direct branch
// instructions.
fixup_arm_branch,
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=120635&r1=120634&r2=120635&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Dec 1 18:28:45 2010
@@ -1184,8 +1184,9 @@
// assembler.
let neverHasSideEffects = 1, isReMaterializable = 1 in
// The 'adr' mnemonic encodes differently if the label is before or after
-// the instruction.
-def ADRadd : AI1<0b0100, (outs GPR:$Rd), (ins adrlabel:$label),
+// the instruction. The {24-21} opcode bits are set by the fixup, as we don't
+// know until then which form of the instruction will be used.
+def ADR : AI1<0, (outs GPR:$Rd), (ins adrlabel:$label),
MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
bits<4> Rd;
bits<12> label;
@@ -1195,23 +1196,8 @@
let Inst{15-12} = Rd;
let Inst{11-0} = label;
}
-def ADRsub : AI1<0b0010, (outs GPR:$Rd), (ins adrlabel:$label),
- MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
- bits<4> Rd;
- bits<12> label;
- let Inst{27-25} = 0b001;
- let Inst{20} = 0;
- let Inst{19-16} = 0b1111;
- let Inst{15-12} = Rd;
- let Inst{11-0} = label;
-}
-
-// FIXME: This should be a pseudo lowered to one of the above at MC lowering
-// time. It may be interesting determining which of the two. Perhaps a fixup
-// will be needed to do so? That would be kinda fugly.
-def LEApcrel : AXI1<0, (outs GPR:$Rd), (ins i32imm:$label, pred:$p),
- MiscFrm, IIC_iALUi,
- "adr${p}\t$Rd, #$label", []>;
+def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
+ Size4Bytes, IIC_iALUi, []>;
def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
(ins i32imm:$label, nohash_imm:$id, pred:$p),
Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=120635&r1=120634&r2=120635&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Dec 1 18:28:45 2010
@@ -45,12 +45,13 @@
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[] = {
- // name offset bits flags
- { "fixup_arm_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
- { "fixup_arm_movt_hi16", 0, 16, 0 },
- { "fixup_arm_movw_lo16", 0, 16, 0 },
+ // name off bits flags
+ { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
+ { "fixup_arm_movt_hi16", 0, 16, 0 },
+ { "fixup_arm_movw_lo16", 0, 16, 0 },
};
if (Kind < FirstTargetFixupKind)
@@ -418,14 +419,10 @@
getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpIdx);
-
- // If the destination is an immediate, we have nothing to do.
- if (MO.isImm()) return MO.getImm();
- assert (MO.isExpr() && "Unexpected branch target type!");
+ assert (MO.isExpr() && "Unexpected adr target type!");
const MCExpr *Expr = MO.getExpr();
- MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
+ MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_adr_pcrel_12);
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
-
// All of the information is in the fixup.
return 0;
}
@@ -448,7 +445,7 @@
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
- MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
+ MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12);
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
++MCNumCPRelocations;
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