[llvm-commits] [llvm] r120604 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

[Jim Grosbach]

Author: grosbach
Date: Wed Dec  1 15:09:40 2010
New Revision: 120604

URL: http://llvm.org/viewvc/llvm-project?rev=120604&view=rev
Log:
Use the correct fixup type for ARM VLDR*

Modified:
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=120604&r1=120603&r2=120604&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Dec  1 15:09:40 2010
@@ -658,7 +658,7 @@
   return getAddrModeSOpValue(MI, OpIdx, 1);
 }
 
-/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
+/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand.
 uint32_t ARMMCCodeEmitter::
 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
                     SmallVectorImpl<MCFixup> &Fixups) const {
@@ -676,7 +676,7 @@
 
     assert(MO.isExpr() && "Unexpected machine operand type!");
     const MCExpr *Expr = MO.getExpr();
-    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
+    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_10);
     Fixups.push_back(MCFixup::Create(0, Expr, Kind));
 
     ++MCNumCPRelocations;