[llvm-commits] [llvm] r120407 - in /llvm/trunk/lib/Target/PTX: PTXAsmPrinter.cpp PTXISelDAGToDAG.cpp PTXInstrInfo.td
Che-Liang Chiou
clchiou at gmail.com
Mon Nov 29 23:34:44 PST 2010
Author: clchiou
Date: Tue Nov 30 01:34:44 2010
New Revision: 120407
URL: http://llvm.org/viewvc/llvm-project?rev=120407&view=rev
Log:
ptx: add ld instruction
support register and register-immediate addressing mode
todo: immediate and register-register addressing mode
Modified:
llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp
llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=120407&r1=120406&r2=120407&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Tue Nov 30 01:34:44 2010
@@ -49,6 +49,8 @@
virtual void EmitInstruction(const MachineInstr *MI);
void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
+ void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
+ const char *Modifier = 0);
// autogen'd.
void printInstruction(const MachineInstr *MI, raw_ostream &OS);
@@ -61,7 +63,7 @@
static const char PARAM_PREFIX[] = "__param_";
-static const char *getRegisterTypeName(unsigned RegNo){
+static const char *getRegisterTypeName(unsigned RegNo) {
#define TEST_REGCLS(cls, clsstr) \
if (PTX::cls ## RegisterClass->contains(RegNo)) return # clsstr;
TEST_REGCLS(RRegs32, s32);
@@ -72,8 +74,7 @@
return NULL;
}
-static const char *getInstructionTypeName(const MachineInstr *MI)
-{
+static const char *getInstructionTypeName(const MachineInstr *MI) {
for (int i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (MO.getType() == MachineOperand::MO_Register)
@@ -119,13 +120,13 @@
// Replace "%type" if found
StringRef strref = OS.str();
size_t pos;
- if ((pos = strref.find("%type")) == StringRef::npos) {
- OutStreamer.EmitRawText(strref);
- return;
+ if ((pos = strref.find("%type")) != StringRef::npos) {
+ std::string str = strref;
+ str.replace(pos, /*strlen("%type")==*/5, getInstructionTypeName(MI));
+ strref = StringRef(str);
}
- std::string str = strref;
- str.replace(pos, /*strlen("%type")==*/5, getInstructionTypeName(MI));
- OutStreamer.EmitRawText(StringRef(str));
+
+ OutStreamer.EmitRawText(strref);
}
void PTXAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
@@ -145,6 +146,17 @@
}
}
+void PTXAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
+ raw_ostream &OS, const char *Modifier) {
+ printOperand(MI, opNum, OS);
+
+ if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() == 0)
+ return; // don't print "+0"
+
+ OS << "+";
+ printOperand(MI, opNum+1, OS);
+}
+
void PTXAsmPrinter::EmitFunctionDeclaration() {
// The function label could have already been emitted if two symbols end up
// conflicting due to asm renaming. Detect this and emit an error.
Modified: llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp?rev=120407&r1=120406&r2=120407&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp Tue Nov 30 01:34:44 2010
@@ -14,6 +14,7 @@
#include "PTX.h"
#include "PTXTargetMachine.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/DerivedTypes.h"
using namespace llvm;
@@ -30,9 +31,16 @@
SDNode *Select(SDNode *Node);
+ // Complex Pattern Selectors.
+ bool SelectADDRri(SDValue &Addr, SDValue &Base, SDValue &Offset);
+ bool SelectADDRii(SDValue &Addr, SDValue &Base, SDValue &Offset);
+
// Include the pieces auto'gened from the target description
#include "PTXGenDAGISel.inc"
+ private:
+ bool isImm (const SDValue &operand);
+ bool SelectImm (const SDValue &operand, SDValue &imm);
}; // class PTXDAGToDAGISel
} // namespace
@@ -51,3 +59,54 @@
// SelectCode() is auto'gened
return SelectCode(Node);
}
+
+// Match memory operand of the form [reg+reg] and [reg+imm]
+bool PTXDAGToDAGISel::SelectADDRri(SDValue &Addr, SDValue &Base,
+ SDValue &Offset) {
+ if (Addr.getNumOperands() >= 2 &&
+ isImm(Addr.getOperand(0)) && isImm(Addr.getOperand(1)))
+ return false; // let SelectADDRii handle the [imm+imm] case
+
+ // try [reg+imm] and [imm+reg]
+ if (Addr.getOpcode() == ISD::ADD)
+ for (int i = 0; i < 2; i ++)
+ if (SelectImm(Addr.getOperand(1-i), Offset)) {
+ Base = Addr.getOperand(i);
+ return true;
+ }
+
+ // okay, it's [reg+reg]
+ Base = Addr;
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
+ return true;
+}
+
+// Match memory operand of the form [imm+imm] and [imm]
+bool PTXDAGToDAGISel::SelectADDRii(SDValue &Addr, SDValue &Base,
+ SDValue &Offset) {
+ if (Addr.getOpcode() == ISD::ADD) {
+ return SelectImm(Addr.getOperand(0), Base) &&
+ SelectImm(Addr.getOperand(1), Offset);
+ }
+
+ if (SelectImm(Addr, Base)) {
+ Offset = CurDAG->getTargetConstant(0, MVT::i32);
+ return true;
+ }
+
+ return false;
+}
+
+bool PTXDAGToDAGISel::isImm(const SDValue &operand) {
+ return ConstantSDNode::classof(operand.getNode());
+}
+
+bool PTXDAGToDAGISel::SelectImm(const SDValue &operand, SDValue &imm) {
+ SDNode *node = operand.getNode();
+ if (!ConstantSDNode::classof(node))
+ return false;
+
+ ConstantSDNode *CN = cast<ConstantSDNode>(node);
+ imm = CurDAG->getTargetConstant(*CN->getConstantIntValue(), MVT::i32);
+ return true;
+}
Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=120407&r1=120406&r2=120407&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Tue Nov 30 01:34:44 2010
@@ -18,6 +18,31 @@
include "PTXInstrFormats.td"
//===----------------------------------------------------------------------===//
+// Instruction Pattern Stuff
+//===----------------------------------------------------------------------===//
+
+def load_global : PatFrag<(ops node:$ptr), (load node:$ptr), [{
+ if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
+ if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
+ return PT->getAddressSpace() <= 255;
+ return false;
+}]>;
+
+// Addressing modes.
+def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [], []>;
+def ADDRii : ComplexPattern<i32, 2, "SelectADDRii", [], []>;
+
+// Address operands
+def MEMri : Operand<i32> {
+ let PrintMethod = "printMemOperand";
+ let MIOperandInfo = (ops RRegs32, i32imm);
+}
+def MEMii : Operand<i32> {
+ let PrintMethod = "printMemOperand";
+ let MIOperandInfo = (ops i32imm, i32imm);
+}
+
+//===----------------------------------------------------------------------===//
// PTX Specific Node Definitions
//===----------------------------------------------------------------------===//
@@ -41,6 +66,17 @@
[(set RRegs32:$d, (opnode RRegs32:$a, imm:$b))]>;
}
+multiclass PTX_LD<string opstr, RegisterClass RC, PatFrag pat_load> {
+ def ri : InstPTX<(outs RC:$d),
+ (ins MEMri:$a),
+ !strconcat(opstr, ".%type\t$d, [$a]"),
+ [(set RC:$d, (pat_load ADDRri:$a))]>;
+ def ii : InstPTX<(outs RC:$d),
+ (ins MEMii:$a),
+ !strconcat(opstr, ".%type\t$d, [$a]"),
+ [(set RC:$d, (pat_load ADDRii:$a))]>;
+}
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
@@ -69,6 +105,8 @@
[(set RRegs32:$d, imm:$a)]>;
}
+defm LDg : PTX_LD<"ld.global", RRegs32, load_global>;
+
///===- Control Flow Instructions -----------------------------------------===//
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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