[llvm-commits] [llvm] r120369 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Bill Wendling
isanbard at gmail.com
Mon Nov 29 16:34:08 PST 2010
Author: void
Date: Mon Nov 29 18:34:08 2010
New Revision: 120369
URL: http://llvm.org/viewvc/llvm-project?rev=120369&view=rev
Log:
Add correct encoding for "bl __aeabi_read_tp". However, the asm matcher isn't
able to match this yet.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=120369&r1=120368&r2=120369&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Nov 29 18:34:08 2010
@@ -1265,11 +1265,13 @@
//
// __aeabi_read_tp preserves the registers r1-r3.
-let isCall = 1,
- Defs = [R0, LR], Uses = [SP] in {
+let isCall = 1, Defs = [R0, LR], Uses = [SP] in {
def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
"bl\t__aeabi_read_tp",
- [(set R0, ARMthread_pointer)]>;
+ [(set R0, ARMthread_pointer)]> {
+ // Encoding is 0xf7fffffe.
+ let Inst = 0xf7fffffe;
+ }
}
// SJLJ Exception handling intrinsics
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