[llvm-commits] [llvm] r120334 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

[Bill Wendling]

Author: void
Date: Mon Nov 29 16:37:46 2010
New Revision: 120334

URL: http://llvm.org/viewvc/llvm-project?rev=120334&view=rev
Log:
Thumb encodings for conditional moves.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=120334&r1=120333&r2=120334&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Nov 29 16:37:46 2010
@@ -1210,12 +1210,24 @@
 let neverHasSideEffects = 1 in {
 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
                     "mov", "\t$dst, $rhs", []>,
-              T1Special<{1,0,?,?}>;
+              T1Special<{1,0,?,?}> {
+  bits<4> rhs;
+  bits<4> dst;
+  let Inst{7}   = dst{3};
+  let Inst{6-3} = rhs;
+  let Inst{2-0} = dst{2-0};
+}
 
 let isMoveImm = 1 in
 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
                     "mov", "\t$dst, $rhs", []>,
-              T1General<{1,0,0,?,?}>;
+              T1General<{1,0,0,?,?}> {
+  bits<8> rhs;
+  bits<3> dst;
+  let Inst{10-8} = dst;
+  let Inst{7-0}  = rhs;
+}
+
 } // neverHasSideEffects
 
 // tLEApcrel - Load a pc-relative address into a register without offending the