[llvm-commits] [llvm] r120277 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb.td test/MC/ARM/thumb.s

[Bill Wendling]

Author: void
Date: Sun Nov 28 18:42:50 2010
New Revision: 120277

URL: http://llvm.org/viewvc/llvm-project?rev=120277&view=rev
Log:
Add Thumb encodings for REV instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/test/MC/ARM/thumb.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=120277&r1=120276&r2=120277&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Sun Nov 28 18:42:50 2010
@@ -1028,30 +1028,48 @@
 }
 
 // Swaps
-def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
-                "rev", "\t$dst, $src",
-                [(set tGPR:$dst, (bswap tGPR:$src))]>,
+def tREV : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
+                "rev", "\t$Rd, $Rm",
+                [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
                 Requires<[IsThumb, IsThumb1Only, HasV6]>,
-           T1Misc<{1,0,1,0,0,0,?}>;
+           T1Misc<{1,0,1,0,0,0,?}> {
+  // A8.6.134
+  bits<3> Rm;
+  bits<3> Rd;
+  let Inst{5-3} = Rm;
+  let Inst{2-0} = Rd;
+}
 
-def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
-                  "rev16", "\t$dst, $src",
-             [(set tGPR:$dst,
-                   (or (and (srl tGPR:$src, (i32 8)), 0xFF),
-                       (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
-                           (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
-                               (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
+def tREV16 : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
+                  "rev16", "\t$Rd, $Rm",
+             [(set tGPR:$Rd,
+                   (or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
+                       (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
+                           (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
+                               (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
                 Requires<[IsThumb, IsThumb1Only, HasV6]>,
-             T1Misc<{1,0,1,0,0,1,?}>;
+             T1Misc<{1,0,1,0,0,1,?}> {
+  // A8.6.135
+  bits<3> Rm;
+  bits<3> Rd;
+  let Inst{5-3} = Rm;
+  let Inst{2-0} = Rd;
+}
 
-def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
-                  "revsh", "\t$dst, $src",
-                  [(set tGPR:$dst,
+def tREVSH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
+                  "revsh", "\t$Rd, $Rm",
+                  [(set tGPR:$Rd,
                         (sext_inreg
-                          (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
-                              (shl tGPR:$src, (i32 8))), i16))]>,
+                          (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
+                              (shl tGPR:$Rm, (i32 8))), i16))]>,
                   Requires<[IsThumb, IsThumb1Only, HasV6]>,
-             T1Misc<{1,0,1,0,1,1,?}>;
+             T1Misc<{1,0,1,0,1,1,?}> {
+  // A8.6.135
+  bits<3> Rm;
+  bits<3> Rd;
+  let Inst{5-3} = Rm;
+  let Inst{2-0} = Rd;
+}
 
 // rotate right register
 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,

Modified: llvm/trunk/test/MC/ARM/thumb.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb.s?rev=120277&r1=120276&r2=120277&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb.s (original)
+++ llvm/trunk/test/MC/ARM/thumb.s Sun Nov 28 18:42:50 2010
@@ -1,4 +1,4 @@
-@ RUN: llvm-mc -triple thumb-apple-darwin -show-encoding < %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv6-apple-darwin -show-encoding < %s | FileCheck %s
         .code 16
 
 @ CHECK: cmp	r1, r2               @ encoding: [0x91,0x42]
@@ -12,3 +12,10 @@
 
 @ CHECK: blx	r9                   @ encoding: [0xc8,0x47]
 	blx	r9
+
+@ CHECK: rev	r2, r3               @ encoding: [0x1a,0xba]
+@ CHECK: rev16	r3, r4               @ encoding: [0x63,0xba]
+@ CHECK: revsh	r5, r6               @ encoding: [0xf5,0xba]
+        rev     r2, r3
+        rev16   r3, r4
+        revsh   r5, r6