[llvm-commits] [llvm] r120028 - in /llvm/trunk: lib/Target/README.txt lib/Transforms/InstCombine/InstCombineShifts.cpp test/Transforms/InstCombine/shift.ll

[Chris Lattner]

On Nov 23, 2010, at 10:52 AM, Benjamin Kramer wrote:

> Author: d0k
> Date: Tue Nov 23 12:52:42 2010
> New Revision: 120028
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=120028&view=rev
> Log:
> InstCombine: Reduce "X shift (A srem B)" to "X shift (A urem B)" iff B is positive.
> 
> This allows to transform the rem in "1 << ((int)x % 8);" to an and.

Nifty.  Could this be generalized into SimplifyDemandedBits?  It seems that the srem simplifies because the shift doesn't need all the result bits of it.

-Chris

> 
> Modified:
>    llvm/trunk/lib/Target/README.txt
>    llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp
>    llvm/trunk/test/Transforms/InstCombine/shift.ll
> 
> Modified: llvm/trunk/lib/Target/README.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=120028&r1=120027&r2=120028&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/README.txt (original)
> +++ llvm/trunk/lib/Target/README.txt Tue Nov 23 12:52:42 2010
> @@ -1698,22 +1698,14 @@
> //===---------------------------------------------------------------------===//
> 
> Missed instcombine transformation:
> -define i32 @a(i32 %x) nounwind readnone {
> -entry:
> -  %rem = srem i32 %x, 32
> -  %shl = shl i32 1, %rem
> -  ret i32 %shl
> -}
> -
> -The srem can be transformed to an and because if x is negative, the shift is
> -undefined.  Here's a more general case that occurs on 64-bit targets:
> 
>   %382 = srem i32 %tmp14.i, 64                    ; [#uses=1]
>   %383 = zext i32 %382 to i64                     ; [#uses=1]
>   %384 = shl i64 %381, %383                       ; [#uses=1]
>   %385 = icmp slt i32 %tmp14.i, 64                ; [#uses=1]
> 
> -Testcase derived from 403.gcc.
> +The srem can be transformed to an and because if x is negative, the shift is
> +undefined.  Testcase derived from 403.gcc.
> 
> //===---------------------------------------------------------------------===//
> 
> 
> Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp?rev=120028&r1=120027&r2=120028&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp (original)
> +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Tue Nov 23 12:52:42 2010
> @@ -53,6 +53,21 @@
>   if (ConstantInt *CUI = dyn_cast<ConstantInt>(Op1))
>     if (Instruction *Res = FoldShiftByConstant(Op0, CUI, I))
>       return Res;
> +
> +  // X shift (A srem B) -> X shift (A urem B) iff B is positive.
> +  // Because shifts by negative values are undefined.
> +  if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Op1))
> +    if (BO->getOpcode() == Instruction::SRem && BO->getType()->isIntegerTy()) {
> +      // Make sure the divisor's sign bit is zero.
> +      APInt Mask = APInt::getSignBit(BO->getType()->getPrimitiveSizeInBits());
> +      if (MaskedValueIsZero(BO->getOperand(1), Mask)) {
> +        Value *URem = Builder->CreateURem(BO->getOperand(0), BO->getOperand(1),
> +                                          BO->getName());
> +        I.setOperand(1, URem);
> +        return &I;
> +      }
> +    }
> +
>   return 0;
> }
> 
> 
> Modified: llvm/trunk/test/Transforms/InstCombine/shift.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shift.ll?rev=120028&r1=120027&r2=120028&view=diff
> ==============================================================================
> --- llvm/trunk/test/Transforms/InstCombine/shift.ll (original)
> +++ llvm/trunk/test/Transforms/InstCombine/shift.ll Tue Nov 23 12:52:42 2010
> @@ -441,3 +441,14 @@
> ; CHECK:  %ins = or i128 %tmp23, %A
> ; CHECK:  %tmp46 = trunc i128 %ins to i64
> }
> +
> +define i32 @test38(i32 %x) nounwind readnone {
> +entry:
> +  %rem = srem i32 %x, 32
> +  %shl = shl i32 1, %rem
> +  ret i32 %shl
> +; CHECK: @test38
> +; CHECK-NOT: srem
> +; CHECK: ret i32
> +}
> +
> 
> 
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