[llvm-commits] [llvm] r119801 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

[Owen Anderson]

Author: resistor
Date: Fri Nov 19 07:11:50 2010
New Revision: 119801

URL: http://llvm.org/viewvc/llvm-project?rev=119801&view=rev
Log:
Fix decoding ambiguities of stdrex and ldrex.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=119801&r1=119800&r2=119801&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Nov 19 07:11:50 2010
@@ -2754,10 +2754,8 @@
   
   bits<4> Rn;
   bits<4> Rt;
-  bits<8> imm;
   let Inst{19-16} = Rn{3-0};
   let Inst{15-12} = Rt{3-0};
-  let Inst{7-0}   = imm{7-0};
 }
 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
                 InstrItinClass itin, string opc, string asm, string cstr,
@@ -2772,11 +2770,9 @@
   bits<4> Rd;
   bits<4> Rn;
   bits<4> Rt;
-  bits<8> imm;
   let Inst{11-8}  = Rd{3-0};
   let Inst{19-16} = Rn{3-0};
   let Inst{15-12} = Rt{3-0};
-  let Inst{7-0}   = imm{7-0};
 }
 
 let mayLoad = 1 in {