[llvm-commits] [llvm] r119767 - in /llvm/trunk/lib/Target/ARM: ARMCodeEmitter.cpp ARMInstrInfo.td ARMMCCodeEmitter.cpp

[Jim Grosbach]

"And add bits {31-28} encoding for ARM BLX instructions"

That part was supposed to be a separate commit. Darn wildcards. Oh, well.


On Nov 18, 2010, at 4:27 PM, Jim Grosbach wrote:

> Author: grosbach
> Date: Thu Nov 18 18:27:09 2010
> New Revision: 119767
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=119767&view=rev
> Log:
> Minor cleanups to a few llvm_unreachable() calls.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
>    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
>    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=119767&r1=119766&r2=119767&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Thu Nov 18 18:27:09 2010
> @@ -378,12 +378,8 @@
>     emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
>   else if (MO.isMBB())
>     emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
> -  else {
> -#ifndef NDEBUG
> -    errs() << MO;
> -#endif
> -    llvm_unreachable(0);
> -  }
> +  else
> +    llvm_unreachable("Unable to encode MachineOperand!");
>   return 0;
> }
> 
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=119767&r1=119766&r2=119767&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Nov 18 18:27:09 2010
> @@ -1274,12 +1274,13 @@
>                 [(ARMcall GPR:$func)]>,
>             Requires<[IsARM, HasV5T, IsNotDarwin]> {
>     bits<4> func;
> -    let Inst{27-4} = 0b000100101111111111110011;
> +    let Inst{31-4} = 0b1110000100101111111111110011;
>     let Inst{3-0}   = func;
>   }
> 
>   // ARMv4T
>   // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
> +  // FIXME: x2 insn patterns like this need to be pseudo instructions.
>   def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
>                   IIC_Br, "mov\tlr, pc\n\tbx\t$func",
>                   [(ARMcall_nolink tGPR:$func)]>,
> @@ -1327,7 +1328,7 @@
>                 IIC_Br, "blx\t$func",
>                 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
>     bits<4> func;
> -    let Inst{27-4} = 0b000100101111111111110011;
> +    let Inst{31-4} = 0b1110000100101111111111110011;
>     let Inst{3-0}   = func;
>   }
> 
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=119767&r1=119766&r2=119767&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Nov 18 18:27:09 2010
> @@ -316,10 +316,7 @@
>                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
>   }
> 
> -#ifndef NDEBUG
> -  errs() << MO;
> -#endif
> -  llvm_unreachable(0);
> +  llvm_unreachable("Unable to encode MCOperand!");
>   return 0;
> }
> 
> @@ -421,8 +418,8 @@
>     }
>     Fixups.push_back(MCFixup::Create(0, Expr, Kind));
>     return 0;
> -  }
> -  llvm_unreachable("Unsupported MCExpr type in MCOperand");
> +  };
> +  llvm_unreachable("Unsupported MCExpr type in MCOperand!");
>   return 0;
> }
> 
> 
> 
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