[llvm-commits] [llvm] r119749 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll

[Tanya Lattner]

Author: tbrethou
Date: Thu Nov 18 16:06:46 2010
New Revision: 119749

URL: http://llvm.org/viewvc/llvm-project?rev=119749&view=rev
Log:
Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on illegal types (vector should be split first).
Added test case.


Added:
    llvm/trunk/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=119749&r1=119748&r2=119749&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Nov 18 16:06:46 2010
@@ -4985,7 +4985,8 @@
   EVT VT = N->getValueType(0);
 
   // Nothing to be done for scalar shifts.
-  if (! VT.isVector())
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  if (!VT.isVector() || !TLI.isTypeLegal(VT))
     return SDValue();
 
   assert(ST->hasNEON() && "unexpected vector shift");

Added: llvm/trunk/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll?rev=119749&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2010-11-17-DAGCombineShiftBug.ll Thu Nov 18 16:06:46 2010
@@ -0,0 +1,8 @@
+; RUN: llc < %s -march=arm -mattr=+neon
+define void @lshrIllegalType(<8 x i32>* %A) nounwind {
+       %tmp1 = load <8 x i32>* %A
+       %tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
+       store <8 x i32> %tmp2, <8 x i32>* %A
+       ret void
+}
+