[llvm-commits] [llvm] r119725 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMBaseInstrInfo.h lib/Target/ARM/ARMBaseRegisterInfo.h lib/Target/ARM/ARMFrameInfo.cpp test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll test/CodeGen/ARM/str_pre-2.ll test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
Evan Cheng
evan.cheng at apple.com
Thu Nov 18 12:51:12 PST 2010
On Nov 18, 2010, at 11:40 AM, Eric Christopher wrote:
>
> +
> + // It's illegal to emit pop instruction without operands.
> + if (NumRegs)
> + MBB.insert(MI, &*MIB);
> + else
> + MF.DeleteMachineInstr(MIB);
Couldn't the code avoid creating the instruction in the first place?
Evan
> +}
> +
> +bool
> +ARMBaseInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
> + MachineBasicBlock::iterator MI,
> + const std::vector<CalleeSavedInfo> &CSI,
> + const TargetRegisterInfo *TRI) const {
> + if (CSI.empty())
> + return false;
> +
> + MachineFunction &MF = *MBB.getParent();
> + ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
> + bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
> + DebugLoc DL = MI->getDebugLoc();
> +
> + unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
> + unsigned FltOpc = ARM::VLDMDIA_UPD;
> + emitPopInst(MBB, MI, CSI, FltOpc, isVarArg, &isARMArea3Register);
> + emitPopInst(MBB, MI, CSI, PopOpc, isVarArg, &isARMArea2Register);
> + emitPopInst(MBB, MI, CSI, PopOpc, isVarArg, &isARMArea1Register);
>
> - // Insert the spill to the stack frame. The register is killed at the spill
> - //
> - const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
> - storeRegToStackSlot(MBB, MI, Reg, isKill,
> - CSI[i].getFrameIdx(), RC, TRI);
> - }
> return true;
> }
>
> +
> // Branch analysis.
> bool
> ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
> @@ -2195,7 +2281,7 @@
> case ARM::VSTMQIA:
> case ARM::VSTMQDB:
> return 2;
> - }
> + }
> }
>
> bool ARMBaseInstrInfo::
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=119725&r1=119724&r2=119725&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Thu Nov 18 13:40:05 2010
> @@ -211,6 +211,21 @@
> const std::vector<CalleeSavedInfo> &CSI,
> const TargetRegisterInfo *TRI) const;
>
> + bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
> + MachineBasicBlock::iterator MI,
> + const std::vector<CalleeSavedInfo> &CSI,
> + const TargetRegisterInfo *TRI) const;
> +
> +private:
> + void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
> + const std::vector<CalleeSavedInfo> &CSI, unsigned Opc,
> + bool isVarArg, bool(*Func)(unsigned, bool)) const;
> + void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
> + const std::vector<CalleeSavedInfo> &CSI, unsigned Opc,
> + bool(*Func)(unsigned, bool)) const;
> +
> +
> +public:
> // Branch analysis.
> virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
> MachineBasicBlock *&FBB,
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=119725&r1=119724&r2=119725&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Thu Nov 18 13:40:05 2010
> @@ -44,6 +44,45 @@
> }
> }
>
> +/// isARMArea1Register - Returns true if the register is a low register (r0-r7)
> +/// or a stack/pc register that we should push/pop.
> +static inline bool isARMArea1Register(unsigned Reg, bool isDarwin) {
> + using namespace ARM;
> + switch (Reg) {
> + case R0: case R1: case R2: case R3:
> + case R4: case R5: case R6: case R7:
> + case LR: case SP: case PC:
> + return true;
> + case R8: case R9: case R10: case R11:
> + // For darwin we want r7 and lr to be next to each other.
> + return !isDarwin;
> + default:
> + return false;
> + }
> +}
> +
> +static inline bool isARMArea2Register(unsigned Reg, bool isDarwin) {
> + using namespace ARM;
> + switch (Reg) {
> + case R8: case R9: case R10: case R11:
> + // Darwin has this second area.
> + return isDarwin;
> + default:
> + return false;
> + }
> +}
> +
> +static inline bool isARMArea3Register(unsigned Reg, bool isDarwin) {
> + using namespace ARM;
> + switch (Reg) {
> + case D15: case D14: case D13: case D12:
> + case D11: case D10: case D9: case D8:
> + return true;
> + default:
> + return false;
> + }
> +}
> +
> class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
> protected:
> const ARMBaseInstrInfo &TII;
>
> Modified: llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp?rev=119725&r1=119724&r2=119725&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp Thu Nov 18 13:40:05 2010
> @@ -20,43 +20,6 @@
>
> using namespace llvm;
>
> -/// Move iterator past the next bunch of callee save load / store ops for
> -/// the particular spill area (1: integer area 1, 2: integer area 2,
> -/// 3: fp area, 0: don't care).
> -static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
> - MachineBasicBlock::iterator &MBBI,
> - int Opc1, int Opc2, unsigned Area,
> - const ARMSubtarget &STI) {
> - while (MBBI != MBB.end() &&
> - ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
> - MBBI->getOperand(1).isFI()) {
> - if (Area != 0) {
> - bool Done = false;
> - unsigned Category = 0;
> - switch (MBBI->getOperand(0).getReg()) {
> - case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
> - case ARM::LR:
> - Category = 1;
> - break;
> - case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
> - Category = STI.isTargetDarwin() ? 2 : 1;
> - break;
> - case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
> - case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
> - Category = 3;
> - break;
> - default:
> - Done = true;
> - break;
> - }
> - if (Done || Category != Area)
> - break;
> - }
> -
> - ++MBBI;
> - }
> -}
> -
> static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
> for (unsigned i = 0; CSRegs[i]; ++i)
> if (Reg == CSRegs[i])
> @@ -67,11 +30,21 @@
> static bool isCSRestore(MachineInstr *MI,
> const ARMBaseInstrInfo &TII,
> const unsigned *CSRegs) {
> - return ((MI->getOpcode() == (int)ARM::VLDRD ||
> - MI->getOpcode() == (int)ARM::LDRi12 ||
> - MI->getOpcode() == (int)ARM::t2LDRi12) &&
> - MI->getOperand(1).isFI() &&
> - isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
> + // Integer spill area is handled with "pop".
> + if (MI->getOpcode() == ARM::LDMIA_RET ||
> + MI->getOpcode() == ARM::t2LDMIA_RET ||
> + MI->getOpcode() == ARM::LDMIA_UPD ||
> + MI->getOpcode() == ARM::t2LDMIA_UPD ||
> + MI->getOpcode() == ARM::VLDMDIA_UPD) {
> + // The first two operands are predicates. The last two are
> + // imp-def and imp-use of SP. Check everything in between.
> + for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
> + if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
> + return false;
> + return true;
> + }
> +
> + return false;
> }
>
> static void
> @@ -154,11 +127,10 @@
> DPRCSSize += 8;
> }
> }
> -
> - // Build the new SUBri to adjust SP for integer callee-save spill area 1.
> - emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
> - movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI);
> -
> +
> + // Move past area 1.
> + if (GPRCS1Size > 0) MBBI++;
> +
> // Set FP to point to the stack slot that contains the previous FP.
> // For Darwin, FP is R7, which has now been stored in spill area 1.
> // Otherwise, if this is not Darwin, all the callee-saved registers go
> @@ -172,14 +144,10 @@
> .addFrameIndex(FramePtrSpillFI).addImm(0);
> AddDefaultCC(AddDefaultPred(MIB));
> }
> -
> - // Build the new SUBri to adjust SP for integer callee-save spill area 2.
> - emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
> -
> - // Build the new SUBri to adjust SP for FP callee-save spill area.
> - movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 2, STI);
> - emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
> -
> +
> + // Move past area 2.
> + if (GPRCS2Size > 0) MBBI++;
> +
> // Determine starting offsets of spill areas.
> unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
> unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
> @@ -191,7 +159,9 @@
> AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
> AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
>
> - movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
> + // Move past area 3.
> + if (DPRCSSize > 0) MBBI++;
> +
> NumBytes = DPRCSOffset;
> if (NumBytes) {
> // Adjust SP after all the callee-save spills.
> @@ -325,17 +295,10 @@
> } else if (NumBytes)
> emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
>
> - // Move SP to start of integer callee save spill area 2.
> - movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
> - emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
> -
> - // Move SP to start of integer callee save spill area 1.
> - movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 2, STI);
> - emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
> -
> - // Move SP to SP upon entry to the function.
> - movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI);
> - emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
> + // Increment past our save areas.
> + if (AFI->getDPRCalleeSavedAreaSize()) MBBI++;
> + if (AFI->getGPRCalleeSavedArea2Size()) MBBI++;
> + if (AFI->getGPRCalleeSavedArea1Size()) MBBI++;
> }
>
> if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
>
> Modified: llvm/trunk/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll?rev=119725&r1=119724&r2=119725&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll Thu Nov 18 13:40:05 2010
> @@ -3,7 +3,7 @@
> ; LDM instruction, was causing an assertion failure because the microop count
> ; was being treated as an instruction count.
>
> -; CHECK: ldmia
> +; CHECK: push
> ; CHECK: ldmia
> ; CHECK: ldmia
> ; CHECK: ldmia
>
> Modified: llvm/trunk/test/CodeGen/ARM/str_pre-2.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/str_pre-2.ll?rev=119725&r1=119724&r2=119725&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/str_pre-2.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/str_pre-2.ll Thu Nov 18 13:40:05 2010
> @@ -4,8 +4,8 @@
>
> define i64 @t(i64 %a) nounwind readonly {
> entry:
> -; CHECK: str lr, [sp, #-4]!
> -; CHECK: ldr lr, [sp], #4
> +; CHECK: push {lr}
> +; CHECK: ldmia sp!, {pc}
> %0 = load i64** @b, align 4
> %1 = load i64* %0, align 4
> %2 = mul i64 %1, %a
>
> Modified: llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll?rev=119725&r1=119724&r2=119725&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll (original)
> +++ llvm/trunk/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll Thu Nov 18 13:40:05 2010
> @@ -39,7 +39,7 @@
> ; CHECK: ittt eq
> ; CHECK: moveq r0
> ; CHECK-NOT: LBB0_
> -; CHECK: ldreq
> +; CHECK: popeq
> ; CHECK: popeq
> switch i32 undef, label %bb7 [
> i32 37, label %bb43
>
>
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