[llvm-commits] [llvm] r119559 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp ARMInstrInfo.td

[Jim Grosbach]

Author: grosbach
Date: Wed Nov 17 15:05:55 2010
New Revision: 119559

URL: http://llvm.org/viewvc/llvm-project?rev=119559&view=rev
Log:
Make the ARM BR_JTadd instruction an explicit pseudo and lower it properly
in the MC lowering process.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=119559&r1=119558&r2=119559&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Nov 17 15:05:55 2010
@@ -938,8 +938,7 @@
   }
   case ARM::tBR_JTr:
   case ARM::BR_JTr:
-  case ARM::BR_JTm:
-  case ARM::BR_JTadd: {
+  case ARM::BR_JTm: {
     // Lower and emit the instruction itself, then the jump table following it.
     MCInst TmpInst;
     // FIXME: The branch instruction is really a pseudo. We should xform it
@@ -949,6 +948,25 @@
     EmitJumpTable(MI);
     return;
   }
+  case ARM::BR_JTadd: {
+    // Lower and emit the instruction itself, then the jump table following it.
+    // add pc, target, idx
+    MCInst AddInst;
+    AddInst.setOpcode(ARM::ADDrr);
+    AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
+    AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+    AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
+    // Add predicate operands.
+    AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+    AddInst.addOperand(MCOperand::CreateReg(0));
+    // Add 's' bit operand (always reg0 for this)
+    AddInst.addOperand(MCOperand::CreateReg(0));
+    OutStreamer.EmitInstruction(AddInst);
+
+    // Output the data for the jump table itself
+    EmitJumpTable(MI);
+    return;
+  }
   case ARM::TRAP: {
     // Non-Darwin binutils don't yet support the "trap" mnemonic.
     // FIXME: Remove this special case when they do.

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=119559&r1=119558&r2=119559&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 17 15:05:55 2010
@@ -1437,16 +1437,11 @@
       let Inst{24}    = 1; // P bit
       let Inst{27-25} = 0b011;
     }
-    def BR_JTadd : JTI<(outs),
-                     (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
-                      IIC_Br, "add\tpc, $target, $idx$jt",
-                      [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
-                        imm:$id)]> {
-      let Inst{15-12} = 0b1111;
-      let Inst{20}    = 0; // S bit
-      let Inst{24-21} = 0b0100;
-      let Inst{27-25} = 0b000;
-    }
+    def BR_JTadd : PseudoInst<(outs),
+                   (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
+                   IIC_Br, "",
+                   [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
+                     imm:$id)]>;
     } // isNotDuplicable = 1, isIndirectBranch = 1
   } // isBarrier = 1