[llvm-commits] [llvm] r119403 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrThumb2.td

[Bill Wendling]

Author: void
Date: Tue Nov 16 17:44:49 2010
New Revision: 119403

URL: http://llvm.org/viewvc/llvm-project?rev=119403&view=rev
Log:
Use the correct variable names so that the encodings will be correct.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=119403&r1=119402&r2=119403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Nov 16 17:44:49 2010
@@ -1870,9 +1870,9 @@
 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
     hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
-                                      reglist:$dsts, variable_ops),
+                                      reglist:$regs, variable_ops),
                      IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
-                     "ldmia${p}\t$Rn!, $dsts",
+                     "ldmia${p}\t$Rn!, $regs",
                      "$Rn = $wb", []> {
   let Inst{24-23} = 0b01;       // Increment After
   let Inst{21}    = 1;          // Writeback

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=119403&r1=119402&r2=119403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Nov 16 17:44:49 2010
@@ -2760,9 +2760,9 @@
 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
     hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
 def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
-                                        reglist:$dsts, variable_ops),
+                                        reglist:$regs, variable_ops),
                         IIC_iLoad_mBr,
-                        "ldmia${p}.w\t$Rn!, $dsts",
+                        "ldmia${p}.w\t$Rn!, $regs",
                         "$Rn = $wb", []> {
   bits<4>  Rn;
   bits<16> regs;