[llvm-commits] [llvm] r119323 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td ARMInstrThumb2.td

[Bill Wendling]

Author: void
Date: Mon Nov 15 20:08:45 2010
New Revision: 119323

URL: http://llvm.org/viewvc/llvm-project?rev=119323&view=rev
Log:
- Remove dead patterns.
- Add encodings to the *LDMIA_RET instrs. Probably not needed...

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=119323&r1=119322&r2=119323&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Nov 15 20:08:45 2010
@@ -834,38 +834,6 @@
   let Inst{19-16} = Rn;
   let Inst{15-0}  = regs;
 }
-class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
-             string asm, string cstr, list<dag> pattern>
-  : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
-       asm, cstr, pattern> {
-  bits<4> p;
-  bits<16> dsts;
-  bits<4> Rn;
-  bits<2> amode;
-  let Inst{31-28} = p;
-  let Inst{27-25} = 0b100;
-  let Inst{24-23} = amode;
-  let Inst{22}    = 0; // S bit
-  let Inst{20}    = 1; // L bit
-  let Inst{19-16} = Rn;
-  let Inst{15-0}  = dsts;
-}
-class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
-             string asm, string cstr, list<dag> pattern>
-  : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
-       asm, cstr, pattern> {
-  bits<4> p;
-  bits<16> srcs;
-  bits<4> Rn;
-  bits<2> amode;
-  let Inst{31-28} = p;
-  let Inst{27-25} = 0b100;
-  let Inst{24-23} = amode;
-  let Inst{22}    = 0; // S bit
-  let Inst{20}    = 0; // L bit
-  let Inst{19-16} = Rn;
-  let Inst{15-0}  = srcs;
-}
 
 // Unsigned multiply, multiply-accumulate instructions.
 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=119323&r1=119322&r2=119323&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Nov 15 20:08:45 2010
@@ -1869,16 +1869,16 @@
 // FIXME: Should pc be an implicit operand like PICADD, etc?
 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
     hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
-def LDMIA_RET : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
-                                        reglist:$dsts, variable_ops),
-                       IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
-                       "ldmia${p}\t$Rn!, $dsts",
-                       "$Rn = $wb", []> {
-  let Inst{24-23} = 0b01;     // Increment After
-  let Inst{21}    = 1;        // Writeback
+def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
+                                      reglist:$dsts, variable_ops),
+                     IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
+                     "ldmia${p}\t$Rn!, $dsts",
+                     "$Rn = $wb", []> {
+  let Inst{24-23} = 0b01;       // Increment After
+  let Inst{21}    = 1;          // Writeback
+  let Inst{20}    = 1;          // Load
 }
 
-
 //===----------------------------------------------------------------------===//
 //  Move Instructions.
 //

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=119323&r1=119322&r2=119323&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Nov 15 20:08:45 2010
@@ -2764,9 +2764,17 @@
                         IIC_iLoad_mBr,
                         "ldmia${p}.w\t$Rn!, $dsts",
                         "$Rn = $wb", []> {
-  let Inst{24-23} = 0b01; // IA: '01', DB: '10'
-  let Inst{21}    = 1; // The W bit.
-  let Inst{20}    = 1; // Load
+  bits<4>  Rn;
+  bits<16> regs;
+ 
+  let Inst{31-27} = 0b11101;
+  let Inst{26-25} = 0b00;
+  let Inst{24-23} = 0b01;     // Increment After
+  let Inst{22}    = 0;
+  let Inst{21}    = 1;        // Writeback
+  let Inst{20}    = L_bit;
+  let Inst{19-16} = Rn;
+  let Inst{15-0}  = regs;
 }
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {