[llvm-commits] [llvm] r118998 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMInstrThumb.td ARMInstrThumb2.td ARMInstrVFP.td
Bill Wendling
isanbard at gmail.com
Sat Nov 13 02:43:34 PST 2010
Author: void
Date: Sat Nov 13 04:43:34 2010
New Revision: 118998
URL: http://llvm.org/viewvc/llvm-project?rev=118998&view=rev
Log:
Convert the modes to lower case.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118998&r1=118997&r2=118998&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Sat Nov 13 04:43:34 2010
@@ -1737,7 +1737,7 @@
multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
InstrItinClass itin, InstrItinClass itin_upd> {
- def IA :
+ def ia :
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
!strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
@@ -1745,7 +1745,7 @@
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def IA_UPD :
+ def ia_UPD :
AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, f, itin_upd,
!strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -1753,7 +1753,7 @@
let Inst{21} = 1; // No writeback
let Inst{20} = L_bit;
}
- def DA :
+ def da :
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
!strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
@@ -1761,7 +1761,7 @@
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def DA_UPD :
+ def da_UPD :
AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, f, itin_upd,
!strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -1769,7 +1769,7 @@
let Inst{21} = 1; // No writeback
let Inst{20} = L_bit;
}
- def DB :
+ def db :
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
!strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
@@ -1777,7 +1777,7 @@
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def DB_UPD :
+ def db_UPD :
AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, f, itin_upd,
!strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -1785,7 +1785,7 @@
let Inst{21} = 1; // No writeback
let Inst{20} = L_bit;
}
- def IB :
+ def ib :
AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, f, itin,
!strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
@@ -1793,7 +1793,7 @@
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def IB_UPD :
+ def ib_UPD :
AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, f, itin_upd,
!strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=118998&r1=118997&r2=118998&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Sat Nov 13 04:43:34 2010
@@ -539,11 +539,11 @@
multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
InstrItinClass itin_upd, bits<6> T1Enc,
bit L_bit> {
- def IA :
+ def ia :
T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>,
T1Encoding<T1Enc>;
- def IA_UPD :
+ def ia_UPD :
T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin_upd, !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
T1Encoding<T1Enc>;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=118998&r1=118997&r2=118998&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Sat Nov 13 04:43:34 2010
@@ -1285,7 +1285,7 @@
multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
InstrItinClass itin_upd, bit L_bit> {
- def IA :
+ def ia :
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
bits<4> Rn;
@@ -1300,7 +1300,7 @@
let Inst{19-16} = Rn;
let Inst{15-0} = regs;
}
- def IA_UPD :
+ def ia_UPD :
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
bits<4> Rn;
@@ -1315,7 +1315,7 @@
let Inst{19-16} = Rn;
let Inst{15-0} = regs;
}
- def DB :
+ def db :
T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
bits<4> Rn;
@@ -1330,7 +1330,7 @@
let Inst{19-16} = Rn;
let Inst{15-0} = regs;
}
- def DB_UPD :
+ def db_UPD :
T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
bits<4> Rn;
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=118998&r1=118997&r2=118998&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Sat Nov 13 04:43:34 2010
@@ -76,7 +76,7 @@
multiclass vfp_ldst_d_mult<string asm, bit L_bit,
InstrItinClass itin, InstrItinClass itin_upd> {
- def IA :
+ def ia :
AXDI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, itin,
!strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
@@ -84,7 +84,7 @@
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def IA_UPD :
+ def ia_UPD :
AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, itin_upd,
!strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -92,7 +92,7 @@
let Inst{21} = 1; // Writeback
let Inst{20} = L_bit;
}
- def DB :
+ def db :
AXDI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, itin,
!strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
@@ -100,7 +100,7 @@
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def DB_UPD :
+ def db_UPD :
AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, itin_upd,
!strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -112,7 +112,7 @@
multiclass vfp_ldst_s_mult<string asm, bit L_bit,
InstrItinClass itin, InstrItinClass itin_upd> {
- def IA :
+ def ia :
AXSI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, itin,
!strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
@@ -120,7 +120,7 @@
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def IA_UPD :
+ def ia_UPD :
AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, itin_upd,
!strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
@@ -128,7 +128,7 @@
let Inst{21} = 1; // Writeback
let Inst{20} = L_bit;
}
- def DB :
+ def db :
AXSI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeNone, itin,
!strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
@@ -136,7 +136,7 @@
let Inst{21} = 0; // No writeback
let Inst{20} = L_bit;
}
- def DB_UPD :
+ def db_UPD :
AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IndexModeUpd, itin_upd,
!strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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