[llvm-commits] [llvm] r118987 - in /llvm/trunk: lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp test/MC/Disassembler/mblaze-tests.txt
Wesley Peck
peckw at wesleypeck.com
Fri Nov 12 21:48:21 PST 2010
Author: peckw
Date: Fri Nov 12 23:48:21 2010
New Revision: 118987
URL: http://llvm.org/viewvc/llvm-project?rev=118987&view=rev
Log:
Fixed error and re-enabled MBlaze MC disassembler tests.
Added:
llvm/trunk/test/MC/Disassembler/mblaze-tests.txt
Modified:
llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
Modified: llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp?rev=118987&r1=118986&r2=118987&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp Fri Nov 12 23:48:21 2010
@@ -492,6 +492,9 @@
uint32_t insn;
uint8_t bytes[4];
+ // We always consume 4 bytes of data
+ size = 4;
+
// We want to read exactly 4 bytes of data.
if (region.readBytes(address, 4, (uint8_t*)bytes, NULL) == -1)
return false;
Added: llvm/trunk/test/MC/Disassembler/mblaze-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/mblaze-tests.txt?rev=118987&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/mblaze-tests.txt (added)
+++ llvm/trunk/test/MC/Disassembler/mblaze-tests.txt Fri Nov 12 23:48:21 2010
@@ -0,0 +1,1079 @@
+# RUN: llvm-mc --disassemble %s -triple=mblaze-unknown-unknown | FileCheck %s
+
+################################################################################
+# Branch instructions
+################################################################################
+
+# CHECK: beq r2, r3
+0x9c 0x02 0x18 0x00
+
+# CHECK: bge r2, r3
+0x9c 0xa2 0x18 0x00
+
+# CHECK: bgt r2, r3
+0x9c 0x82 0x18 0x00
+
+# CHECK: ble r2, r3
+0x9c 0x62 0x18 0x00
+
+# CHECK: blt r2, r3
+0x9c 0x42 0x18 0x00
+
+# CHECK: bne r2, r3
+0x9c 0x22 0x18 0x00
+
+# CHECK: beqd r2, r3
+0x9e 0x02 0x18 0x00
+
+# CHECK: bged r2, r3
+0x9e 0xa2 0x18 0x00
+
+# CHECK: bgtd r2, r3
+0x9e 0x82 0x18 0x00
+
+# CHECK: bled r2, r3
+0x9e 0x62 0x18 0x00
+
+# CHECK: bltd r2, r3
+0x9e 0x42 0x18 0x00
+
+# CHECK: bned r2, r3
+0x9e 0x22 0x18 0x00
+
+# CHECK: br r3
+0x98 0x00 0x18 0x00
+
+# CHECK: bra r3
+0x98 0x08 0x18 0x00
+
+# CHECK: brd r3
+0x98 0x10 0x18 0x00
+
+# CHECK: brad r3
+0x98 0x18 0x18 0x00
+
+# CHECK: brld r15, r3
+0x99 0xf4 0x18 0x00
+
+# CHECK: brald r15, r3
+0x99 0xfc 0x18 0x00
+
+# CHECK: brk r15, r3
+0x99 0xec 0x18 0x00
+
+# CHECK: beqi r2, 0
+0xbc 0x02 0x00 0x00
+
+# CHECK: bgei r2, 0
+0xbc 0xa2 0x00 0x00
+
+# CHECK: bgti r2, 0
+0xbc 0x82 0x00 0x00
+
+ # CHECK: blei r2, 0
+0xbc 0x62 0x00 0x00
+
+# CHECK: blti r2, 0
+0xbc 0x42 0x00 0x00
+
+# CHECK: bnei r2, 0
+0xbc 0x22 0x00 0x00
+
+# CHECK: beqid r2, 0
+0xbe 0x02 0x00 0x00
+
+# CHECK: bgeid r2, 0
+0xbe 0xa2 0x00 0x00
+
+# CHECK: bgtid r2, 0
+0xbe 0x82 0x00 0x00
+
+# CHECK: bleid r2, 0
+0xbe 0x62 0x00 0x00
+
+# CHECK: bltid r2, 0
+0xbe 0x42 0x00 0x00
+
+# CHECK: bneid r2, 0
+0xbe 0x22 0x00 0x00
+
+# CHECK: bri 0
+0xb8 0x00 0x00 0x00
+
+# CHECK: brai 0
+0xb8 0x08 0x00 0x00
+
+# CHECK: brid 0
+0xb8 0x10 0x00 0x00
+
+# CHECK: braid 0
+0xb8 0x18 0x00 0x00
+
+# CHECK: brlid r15, 0
+0xb9 0xf4 0x00 0x00
+
+# CHECK: bralid r15, 0
+0xb9 0xfc 0x00 0x00
+
+# CHECK: brki r15, 0
+0xb9 0xec 0x00 0x00
+
+################################################################################
+# TYPE A instructions
+################################################################################
+
+# CHECK: add r1, r2, r3
+0x00 0x22 0x18 0x00
+
+# CHECK: addc r1, r2, r3
+0x08 0x22 0x18 0x00
+
+# CHECK: addk r1, r2, r3
+0x10 0x22 0x18 0x00
+
+# CHECK: addkc r1, r2, r3
+0x18 0x22 0x18 0x00
+
+# CHECK: and r1, r2, r3
+0x84 0x22 0x18 0x00
+
+# CHECK: andn r1, r2, r3
+0x8c 0x22 0x18 0x00
+
+# CHECK: cmp r1, r2, r3
+0x14 0x22 0x18 0x01
+
+# CHECK: cmpu r1, r2, r3
+0x14 0x22 0x18 0x03
+
+# CHECK: idiv r1, r2, r3
+0x48 0x22 0x18 0x00
+
+# CHECK: idivu r1, r2, r3
+0x48 0x22 0x18 0x02
+
+# CHECK: mul r1, r2, r3
+0x40 0x22 0x18 0x00
+
+# CHECK: mulh r1, r2, r3
+0x40 0x22 0x18 0x01
+
+# CHECK: mulhu r1, r2, r3
+0x40 0x22 0x18 0x03
+
+# CHECK: mulhsu r1, r2, r3
+0x40 0x22 0x18 0x02
+
+# CHECK: or r1, r2, r3
+0x80 0x22 0x18 0x00
+
+# CHECK: rsub r1, r2, r3
+0x04 0x22 0x18 0x00
+
+# CHECK: rsubc r1, r2, r3
+0x0c 0x22 0x18 0x00
+
+# CHECK: rsubk r1, r2, r3
+0x14 0x22 0x18 0x00
+
+# CHECK: rsubkc r1, r2, r3
+0x1c 0x22 0x18 0x00
+
+# CHECK: sext16 r1, r2
+0x90 0x22 0x00 0x61
+
+# CHECK: sext8 r1, r2
+0x90 0x22 0x00 0x60
+
+# CHECK: xor r1, r2, r3
+0x88 0x22 0x18 0x00
+
+# CHECK: or r0, r0, r0
+0x80 0x00 0x00 0x00
+
+################################################################################
+# TYPE B instructions
+################################################################################
+
+# CHECK: addi r1, r2, 15
+0x20 0x22 0x00 0x0f
+
+# CHECK: addic r1, r2, 15
+0x28 0x22 0x00 0x0f
+
+# CHECK: addik r1, r2, 15
+0x30 0x22 0x00 0x0f
+
+# CHECK: addikc r1, r2, 15
+0x38 0x22 0x00 0x0f
+
+# CHECK: andi r1, r2, 15
+0xa4 0x22 0x00 0x0f
+
+# CHECK: andni r1, r2, 15
+0xac 0x22 0x00 0x0f
+
+# CHECK: muli r1, r2, 15
+0x60 0x22 0x00 0x0f
+
+# CHECK: ori r1, r2, 15
+0xa0 0x22 0x00 0x0f
+
+# CHECK: rsubi r1, r2, 15
+0x24 0x22 0x00 0x0f
+
+# CHECK: rsubic r1, r2, 15
+0x2c 0x22 0x00 0x0f
+
+# CHECK: rsubik r1, r2, 15
+0x34 0x22 0x00 0x0f
+
+# CHECK: rsubikc r1, r2, 15
+0x3c 0x22 0x00 0x0f
+
+# CHECK: rtbd r15, 15
+0xb6 0x4f 0x00 0x0f
+
+# CHECK: rted r15, 15
+0xb6 0x8f 0x00 0x0f
+
+# CHECK: rtid r15, 15
+0xb6 0x2f 0x00 0x0f
+
+# CHECK: rtsd r15, 15
+0xb6 0x0f 0x00 0x0f
+
+# CHECK: xori r1, r2, 15
+0xa8 0x22 0x00 0x0f
+
+################################################################################
+# FPU instructions
+################################################################################
+
+# CHECK: fadd r0, r1, r2
+0x58 0x01 0x10 0x00
+
+# CHECK: frsub r0, r1, r2
+0x58 0x01 0x10 0x80
+
+# CHECK: fmul r0, r1, r2
+0x58 0x01 0x11 0x00
+
+# CHECK: fdiv r0, r1, r2
+0x58 0x01 0x11 0x80
+
+# CHECK: fsqrt r0, r1
+0x58 0x01 0x03 0x80
+
+# CHECK: fint r0, r1
+0x58 0x01 0x03 0x00
+
+# CHECK: flt r0, r1
+0x58 0x01 0x02 0x80
+
+# CHECK: fcmp.un r0, r1, r2
+0x58 0x01 0x12 0x00
+
+# CHECK: fcmp.lt r0, r1, r2
+0x58 0x01 0x12 0x10
+
+# CHECK: fcmp.eq r0, r1, r2
+0x58 0x01 0x12 0x20
+
+# CHECK: fcmp.le r0, r1, r2
+0x58 0x01 0x12 0x30
+
+# CHECK: fcmp.gt r0, r1, r2
+0x58 0x01 0x12 0x40
+
+# CHECK: fcmp.ne r0, r1, r2
+0x58 0x01 0x12 0x50
+
+# CHECK: fcmp.ge r0, r1, r2
+0x58 0x01 0x12 0x60
+
+################################################################################
+# IMM instruction processing
+################################################################################
+
+# CHECK: addi r0, r0, 0
+0x20 0x00 0x00 0x00
+
+# CHECK: addi r0, r0, 1
+0x20 0x00 0x00 0x01
+
+# CHECK: addi r0, r0, 2
+0x20 0x00 0x00 0x02
+
+# CHECK: addi r0, r0, 4
+0x20 0x00 0x00 0x04
+
+# CHECK: addi r0, r0, 8
+0x20 0x00 0x00 0x08
+
+# CHECK: addi r0, r0, 16
+0x20 0x00 0x00 0x10
+
+# CHECK: addi r0, r0, 32
+0x20 0x00 0x00 0x20
+
+# CHECK: addi r0, r0, 64
+0x20 0x00 0x00 0x40
+
+# CHECK: addi r0, r0, 128
+0x20 0x00 0x00 0x80
+
+# CHECK: addi r0, r0, 256
+0x20 0x00 0x01 0x00
+
+# CHECK: addi r0, r0, 512
+0x20 0x00 0x02 0x00
+
+# CHECK: addi r0, r0, 1024
+0x20 0x00 0x04 0x00
+
+# CHECK: addi r0, r0, 2048
+0x20 0x00 0x08 0x00
+
+# CHECK: addi r0, r0, 4096
+0x20 0x00 0x10 0x00
+
+# CHECK: addi r0, r0, 8192
+0x20 0x00 0x20 0x00
+
+# CHECK: addi r0, r0, 16384
+0x20 0x00 0x40 0x00
+
+# CHECK: imm 0
+# CHECK: addi r0, r0, -32768
+0xb0 0x00 0x00 0x00 0x20 0x00 0x80 0x00
+
+# CHECK: imm 1
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x00 0x01 0x20 0x00 0x00 0x00
+
+# CHECK: imm 2
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x00 0x02 0x20 0x00 0x00 0x00
+
+# CHECK: imm 4
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x00 0x04 0x20 0x00 0x00 0x00
+
+# CHECK: imm 8
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x00 0x08 0x20 0x00 0x00 0x00
+
+# CHECK: imm 16
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x00 0x10 0x20 0x00 0x00 0x00
+
+# CHECK: imm 32
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x00 0x20 0x20 0x00 0x00 0x00
+
+# CHECK: imm 64
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x00 0x40 0x20 0x00 0x00 0x00
+
+# CHECK: imm 128
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x00 0x80 0x20 0x00 0x00 0x00
+
+# CHECK: imm 256
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x01 0x00 0x20 0x00 0x00 0x00
+
+# CHECK: imm 512
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x02 0x00 0x20 0x00 0x00 0x00
+
+# CHECK: imm 1024
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x04 0x00 0x20 0x00 0x00 0x00
+
+# CHECK: imm 2048
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x08 0x00 0x20 0x00 0x00 0x00
+
+# CHECK: imm 4096
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x10 0x00 0x20 0x00 0x00 0x00
+
+# CHECK: imm 8192
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x20 0x00 0x20 0x00 0x00 0x00
+
+# CHECK: imm 16384
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x40 0x00 0x20 0x00 0x00 0x00
+
+# CHECK: imm -32768
+# CHECK: addi r0, r0, 0
+0xb0 0x00 0x80 0x00 0x20 0x00 0x00 0x00
+
+################################################################################
+# Memory instructions
+################################################################################
+
+# CHECK: lbu r1, r2, r3
+0xc0 0x22 0x18 0x00
+
+# CHECK: lbur r1, r2, r3
+0xc0 0x22 0x1a 0x00
+
+# CHECK: lbui r1, r2, 28
+0xe0 0x22 0x00 0x1c
+
+# CHECK: lhu r1, r2, r3
+0xc4 0x22 0x18 0x00
+
+# CHECK: lhur r1, r2, r3
+0xc4 0x22 0x1a 0x00
+
+# CHECK: lhui r1, r2, 28
+0xe4 0x22 0x00 0x1c
+
+# CHECK: lw r1, r2, r3
+0xc8 0x22 0x18 0x00
+
+# CHECK: lwr r1, r2, r3
+0xc8 0x22 0x1a 0x00
+
+# CHECK: lwi r1, r2, 28
+0xe8 0x22 0x00 0x1c
+
+# CHECK: lwx r1, r2, r3
+0xc8 0x22 0x1c 0x00
+
+# CHECK: sb r1, r2, r3
+0xd0 0x22 0x18 0x00
+
+# CHECK: sbr r1, r2, r3
+0xd0 0x22 0x1a 0x00
+
+# CHECK: sbi r1, r2, 28
+0xf0 0x22 0x00 0x1c
+
+# CHECK: sh r1, r2, r3
+0xd4 0x22 0x18 0x00
+
+# CHECK: shr r1, r2, r3
+0xd4 0x22 0x1a 0x00
+
+# CHECK: shi r1, r2, 28
+0xf4 0x22 0x00 0x1c
+
+# CHECK: sw r1, r2, r3
+0xd8 0x22 0x18 0x00
+
+# CHECK: swr r1, r2, r3
+0xd8 0x22 0x1a 0x00
+
+# CHECK: swi r1, r2, 28
+0xf8 0x22 0x00 0x1c
+
+# CHECK: swx r1, r2, r3
+0xd8 0x22 0x1c 0x00
+
+################################################################################
+# Special instructions
+################################################################################
+
+# CHECK: mfs r0, 0
+0x94 0x00 0x80 0x00
+
+# CHECK: msrclr r0, 0
+0x94 0x11 0x00 0x00
+
+# CHECK: msrset r0, 0
+0x94 0x10 0x00 0x00
+
+# CHECK: mts 0, r0
+0x94 0x00 0xc0 0x00
+
+# CHECK: wdc r0, r1
+0x90 0x00 0x08 0x64
+
+# CHECK: wdc.clear r0, r1
+0x90 0x00 0x08 0x66
+
+# CHECK: wdc.flush r0, r1
+0x90 0x00 0x08 0x74
+
+# CHECK: wic r0, r1
+0x90 0x00 0x08 0x68
+
+################################################################################
+# Shift instructions
+################################################################################
+
+# CHECK: bsrl r1, r2, r3
+0x44 0x22 0x18 0x00
+
+# CHECK: bsra r1, r2, r3
+0x44 0x22 0x1a 0x00
+
+# CHECK: bsll r1, r2, r3
+0x44 0x22 0x1c 0x00
+
+# CHECK: bsrli r1, r2, 0
+0x64 0x22 0x00 0x00
+
+# CHECK: bsrai r1, r2, 0
+0x64 0x22 0x02 0x00
+
+# CHECK: bslli r1, r2, 0
+0x64 0x22 0x04 0x00
+
+# CHECK: sra r1, r2
+0x90 0x22 0x00 0x01
+
+# CHECK: srl r1, r2
+0x90 0x22 0x00 0x41
+
+################################################################################
+# Pattern instructions
+################################################################################
+
+# CHECK: pcmpbf r0, r1, r2
+0x80 0x01 0x14 0x00
+
+# CHECK: pcmpne r0, r1, r2
+0x8c 0x01 0x14 0x00
+
+# CHECK: pcmpeq r0, r1, r2
+0x88 0x01 0x14 0x00
+
+################################################################################
+# Opcode disassembly
+################################################################################
+
+# CHECK: add r0, r0, r0
+0x00 0x00 0x00 0x00
+
+# CHECK: add r1, r1, r1
+0x00 0x21 0x08 0x00
+
+# CHECK: add r2, r2, r2
+0x00 0x42 0x10 0x00
+
+# CHECK: add r3, r3, r3
+0x00 0x63 0x18 0x00
+
+# CHECK: add r4, r4, r4
+0x00 0x84 0x20 0x00
+
+# CHECK: add r5, r5, r5
+0x00 0xa5 0x28 0x00
+
+# CHECK: add r6, r6, r6
+0x00 0xc6 0x30 0x00
+
+# CHECK: add r7, r7, r7
+0x00 0xe7 0x38 0x00
+
+# CHECK: add r8, r8, r8
+0x01 0x08 0x40 0x00
+
+# CHECK: add r9, r9, r9
+0x01 0x29 0x48 0x00
+
+# CHECK: add r10, r10, r10
+0x01 0x4a 0x50 0x00
+
+# CHECK: add r11, r11, r11
+0x01 0x6b 0x58 0x00
+
+# CHECK: add r12, r12, r12
+0x01 0x8c 0x60 0x00
+
+# CHECK: add r13, r13, r13
+0x01 0xad 0x68 0x00
+
+# CHECK: add r14, r14, r14
+0x01 0xce 0x70 0x00
+
+# CHECK: add r15, r15, r15
+0x01 0xef 0x78 0x00
+
+# CHECK: add r16, r16, r16
+0x02 0x10 0x80 0x00
+
+# CHECK: add r17, r17, r17
+0x02 0x31 0x88 0x00
+
+# CHECK: add r18, r18, r18
+0x02 0x52 0x90 0x00
+
+# CHECK: add r19, r19, r19
+0x02 0x73 0x98 0x00
+
+# CHECK: add r20, r20, r20
+0x02 0x94 0xa0 0x00
+
+# CHECK: add r21, r21, r21
+0x02 0xb5 0xa8 0x00
+
+# CHECK: add r22, r22, r22
+0x02 0xd6 0xb0 0x00
+
+# CHECK: add r23, r23, r23
+0x02 0xf7 0xb8 0x00
+
+# CHECK: add r24, r24, r24
+0x03 0x18 0xc0 0x00
+
+# CHECK: add r25, r25, r25
+0x03 0x39 0xc8 0x00
+
+# CHECK: add r26, r26, r26
+0x03 0x5a 0xd0 0x00
+
+# CHECK: add r27, r27, r27
+0x03 0x7b 0xd8 0x00
+
+# CHECK: add r28, r28, r28
+0x03 0x9c 0xe0 0x00
+
+# CHECK: add r29, r29, r29
+0x03 0xbd 0xe8 0x00
+
+# CHECK: add r30, r30, r30
+0x03 0xde 0xf0 0x00
+
+# CHECK: add r31, r31, r31
+0x03 0xff 0xf8 0x00
+
+# CHECK: addi r0, r0, 0
+0x20 0x00 0x00 0x00
+
+# CHECK: addi r0, r0, 1
+0x20 0x00 0x00 0x01
+
+# CHECK: addi r0, r0, 2
+0x20 0x00 0x00 0x02
+
+# CHECK: addi r0, r0, 4
+0x20 0x00 0x00 0x04
+
+# CHECK: addi r0, r0, 8
+0x20 0x00 0x00 0x08
+
+# CHECK: addi r0, r0, 16
+0x20 0x00 0x00 0x10
+
+# CHECK: addi r0, r0, 32
+0x20 0x00 0x00 0x20
+
+# CHECK: addi r0, r0, 64
+0x20 0x00 0x00 0x40
+
+# CHECK: addi r0, r0, 128
+0x20 0x00 0x00 0x80
+
+# CHECK: addi r0, r0, 256
+0x20 0x00 0x01 0x00
+
+# CHECK: addi r0, r0, 512
+0x20 0x00 0x02 0x00
+
+# CHECK: addi r0, r0, 1024
+0x20 0x00 0x04 0x00
+
+# CHECK: addi r0, r0, 2048
+0x20 0x00 0x08 0x00
+
+# CHECK: addi r0, r0, 4096
+0x20 0x00 0x10 0x00
+
+# CHECK: addi r0, r0, 8192
+0x20 0x00 0x20 0x00
+
+# CHECK: addi r0, r0, 16384
+0x20 0x00 0x40 0x00
+
+# CHECK: addi r0, r0, -1
+0x20 0x00 0xff 0xff
+
+# CHECK: addi r0, r0, -2
+0x20 0x00 0xff 0xfe
+
+# CHECK: addi r0, r0, -4
+0x20 0x00 0xff 0xfc
+
+# CHECK: addi r0, r0, -8
+0x20 0x00 0xff 0xf8
+
+# CHECK: addi r0, r0, -16
+0x20 0x00 0xff 0xf0
+
+# CHECK: addi r0, r0, -32
+0x20 0x00 0xff 0xe0
+
+# CHECK: addi r0, r0, -64
+0x20 0x00 0xff 0xc0
+
+# CHECK: addi r0, r0, -128
+0x20 0x00 0xff 0x80
+
+# CHECK: addi r0, r0, -256
+0x20 0x00 0xff 0x00
+
+# CHECK: addi r0, r0, -512
+0x20 0x00 0xfe 0x00
+
+# CHECK: addi r0, r0, -1024
+0x20 0x00 0xfc 0x00
+
+# CHECK: addi r0, r0, -2048
+0x20 0x00 0xf8 0x00
+
+# CHECK: addi r0, r0, -4096
+0x20 0x00 0xf0 0x00
+
+# CHECK: addi r0, r0, -8192
+0x20 0x00 0xe0 0x00
+
+# CHECK: addi r0, r0, -16384
+0x20 0x00 0xc0 0x00
+
+# CHECK: addi r0, r0, -32768
+0x20 0x00 0x80 0x00
+
+################################################################################
+# FSL instructions
+################################################################################
+
+# CHECK: get r0, rfsl0
+0x6c 0x00 0x00 0x00
+
+# CHECK: nget r0, rfsl0
+0x6c 0x00 0x40 0x00
+
+# CHECK: cget r0, rfsl0
+0x6c 0x00 0x20 0x00
+
+# CHECK: ncget r0, rfsl0
+0x6c 0x00 0x60 0x00
+
+# CHECK: tget r0, rfsl0
+0x6c 0x00 0x10 0x00
+
+# CHECK: tnget r0, rfsl0
+0x6c 0x00 0x50 0x00
+
+# CHECK: tcget r0, rfsl0
+0x6c 0x00 0x30 0x00
+
+# CHECK: tncget r0, rfsl0
+0x6c 0x00 0x70 0x00
+
+# CHECK: aget r0, rfsl0
+0x6c 0x00 0x08 0x00
+
+# CHECK: naget r0, rfsl0
+0x6c 0x00 0x48 0x00
+
+# CHECK: caget r0, rfsl0
+0x6c 0x00 0x28 0x00
+
+# CHECK: ncaget r0, rfsl0
+0x6c 0x00 0x68 0x00
+
+# CHECK: taget r0, rfsl0
+0x6c 0x00 0x18 0x00
+
+# CHECK: tnaget r0, rfsl0
+0x6c 0x00 0x58 0x00
+
+# CHECK: tcaget r0, rfsl0
+0x6c 0x00 0x38 0x00
+
+# CHECK: tncaget r0, rfsl0
+0x6c 0x00 0x78 0x00
+
+# CHECK: eget r0, rfsl0
+0x6c 0x00 0x04 0x00
+
+# CHECK: neget r0, rfsl0
+0x6c 0x00 0x44 0x00
+
+# CHECK: ecget r0, rfsl0
+0x6c 0x00 0x24 0x00
+
+# CHECK: necget r0, rfsl0
+0x6c 0x00 0x64 0x00
+
+# CHECK: teget r0, rfsl0
+0x6c 0x00 0x14 0x00
+
+# CHECK: tneget r0, rfsl0
+0x6c 0x00 0x54 0x00
+
+# CHECK: tecget r0, rfsl0
+0x6c 0x00 0x34 0x00
+
+# CHECK: tnecget r0, rfsl0
+0x6c 0x00 0x74 0x00
+
+# CHECK: eaget r0, rfsl0
+0x6c 0x00 0x0c 0x00
+
+# CHECK: neaget r0, rfsl0
+0x6c 0x00 0x4c 0x00
+
+# CHECK: ecaget r0, rfsl0
+0x6c 0x00 0x2c 0x00
+
+# CHECK: necaget r0, rfsl0
+0x6c 0x00 0x6c 0x00
+
+# CHECK: teaget r0, rfsl0
+0x6c 0x00 0x1c 0x00
+
+# CHECK: tneaget r0, rfsl0
+0x6c 0x00 0x5c 0x00
+
+# CHECK: tecaget r0, rfsl0
+0x6c 0x00 0x3c 0x00
+
+# CHECK: tnecaget r0, rfsl0
+0x6c 0x00 0x7c 0x00
+
+# CHECK: getd r0, r1
+0x4c 0x00 0x08 0x00
+
+# CHECK: ngetd r0, r1
+0x4c 0x00 0x0a 0x00
+
+# CHECK: cgetd r0, r1
+0x4c 0x00 0x09 0x00
+
+# CHECK: ncgetd r0, r1
+0x4c 0x00 0x0b 0x00
+
+# CHECK: tgetd r0, r1
+0x4c 0x00 0x08 0x80
+
+# CHECK: tngetd r0, r1
+0x4c 0x00 0x0a 0x80
+
+# CHECK: tcgetd r0, r1
+0x4c 0x00 0x09 0x80
+
+# CHECK: tncgetd r0, r1
+0x4c 0x00 0x0b 0x80
+
+# CHECK: agetd r0, r1
+0x4c 0x00 0x08 0x40
+
+# CHECK: nagetd r0, r1
+0x4c 0x00 0x0a 0x40
+
+# CHECK: cagetd r0, r1
+0x4c 0x00 0x09 0x40
+
+# CHECK: ncagetd r0, r1
+0x4c 0x00 0x0b 0x40
+
+# CHECK: tagetd r0, r1
+0x4c 0x00 0x08 0xc0
+
+# CHECK: tnagetd r0, r1
+0x4c 0x00 0x0a 0xc0
+
+# CHECK: tcagetd r0, r1
+0x4c 0x00 0x09 0xc0
+
+# CHECK: tncagetd r0, r1
+0x4c 0x00 0x0b 0xc0
+
+# CHECK: egetd r0, r1
+0x4c 0x00 0x08 0x20
+
+# CHECK: negetd r0, r1
+0x4c 0x00 0x0a 0x20
+
+# CHECK: ecgetd r0, r1
+0x4c 0x00 0x09 0x20
+
+# CHECK: necgetd r0, r1
+0x4c 0x00 0x0b 0x20
+
+# CHECK: tegetd r0, r1
+0x4c 0x00 0x08 0xa0
+
+# CHECK: tnegetd r0, r1
+0x4c 0x00 0x0a 0xa0
+
+# CHECK: tecgetd r0, r1
+0x4c 0x00 0x09 0xa0
+
+# CHECK: tnecgetd r0, r1
+0x4c 0x00 0x0b 0xa0
+
+# CHECK: eagetd r0, r1
+0x4c 0x00 0x08 0x60
+
+# CHECK: neagetd r0, r1
+0x4c 0x00 0x0a 0x60
+
+# CHECK: ecagetd r0, r1
+0x4c 0x00 0x09 0x60
+
+# CHECK: necagetd r0, r1
+0x4c 0x00 0x0b 0x60
+
+# CHECK: teagetd r0, r1
+0x4c 0x00 0x08 0xe0
+
+# CHECK: tneagetd r0, r1
+0x4c 0x00 0x0a 0xe0
+
+# CHECK: tecagetd r0, r1
+0x4c 0x00 0x09 0xe0
+
+# CHECK: tnecagetd r0, r1
+0x4c 0x00 0x0b 0xe0
+
+# CHECK: put r0, rfsl0
+0x6c 0x00 0x80 0x00
+
+# CHECK: aput r0, rfsl0
+0x6c 0x00 0x88 0x00
+
+# CHECK: cput r0, rfsl0
+0x6c 0x00 0xa0 0x00
+
+# CHECK: caput r0, rfsl0
+0x6c 0x00 0xa8 0x00
+
+# CHECK: nput r0, rfsl0
+0x6c 0x00 0xc0 0x00
+
+# CHECK: naput r0, rfsl0
+0x6c 0x00 0xc8 0x00
+
+# CHECK: ncput r0, rfsl0
+0x6c 0x00 0xe0 0x00
+
+# CHECK: ncaput r0, rfsl0
+0x6c 0x00 0xe8 0x00
+
+# CHECK: tput rfsl0
+0x6c 0x00 0x90 0x00
+
+# CHECK: taput rfsl0
+0x6c 0x00 0x98 0x00
+
+# CHECK: tcput rfsl0
+0x6c 0x00 0xb0 0x00
+
+# CHECK: tcaput rfsl0
+0x6c 0x00 0xb8 0x00
+
+# CHECK: tnput rfsl0
+0x6c 0x00 0xd0 0x00
+
+# CHECK: tnaput rfsl0
+0x6c 0x00 0xd8 0x00
+
+# CHECK: tncput rfsl0
+0x6c 0x00 0xf0 0x00
+
+# CHECK: tncaput rfsl0
+0x6c 0x00 0xf8 0x00
+
+# CHECK: putd r0, r1
+0x4c 0x00 0x0c 0x00
+
+# CHECK: aputd r0, r1
+0x4c 0x00 0x0c 0x40
+
+# CHECK: cputd r0, r1
+0x4c 0x00 0x0d 0x00
+
+# CHECK: caputd r0, r1
+0x4c 0x00 0x0d 0x40
+
+# CHECK: nputd r0, r1
+0x4c 0x00 0x0e 0x00
+
+# CHECK: naputd r0, r1
+0x4c 0x00 0x0e 0x40
+
+# CHECK: ncputd r0, r1
+0x4c 0x00 0x0f 0x00
+
+# CHECK: ncaputd r0, r1
+0x4c 0x00 0x0f 0x40
+
+# CHECK: tputd r1
+0x4c 0x00 0x0c 0x80
+
+# CHECK: taputd r1
+0x4c 0x00 0x0c 0xc0
+
+# CHECK: tcputd r1
+0x4c 0x00 0x0d 0x80
+
+# CHECK: tcaputd r1
+0x4c 0x00 0x0d 0xc0
+
+# CHECK: tnputd r1
+0x4c 0x00 0x0e 0x80
+
+# CHECK: tnaputd r1
+0x4c 0x00 0x0e 0xc0
+
+# CHECK: tncputd r1
+0x4c 0x00 0x0f 0x80
+
+# CHECK: tncaputd r1
+0x4c 0x00 0x0f 0xc0
+
+# CHECK: get r0, rfsl1
+0x6c 0x00 0x00 0x01
+
+# CHECK: get r0, rfsl2
+0x6c 0x00 0x00 0x02
+
+# CHECK: get r0, rfsl3
+0x6c 0x00 0x00 0x03
+
+# CHECK: get r0, rfsl4
+0x6c 0x00 0x00 0x04
+
+# CHECK: get r0, rfsl5
+0x6c 0x00 0x00 0x05
+
+# CHECK: get r0, rfsl6
+0x6c 0x00 0x00 0x06
+
+# CHECK: get r0, rfsl7
+0x6c 0x00 0x00 0x07
+
+# CHECK: get r0, rfsl8
+0x6c 0x00 0x00 0x08
+
+# CHECK: get r0, rfsl9
+0x6c 0x00 0x00 0x09
+
+# CHECK: get r0, rfsl10
+0x6c 0x00 0x00 0x0a
+
+# CHECK: get r0, rfsl11
+0x6c 0x00 0x00 0x0b
+
+# CHECK: get r0, rfsl12
+0x6c 0x00 0x00 0x0c
+
+# CHECK: get r0, rfsl13
+0x6c 0x00 0x00 0x0d
+
+# CHECK: get r0, rfsl14
+0x6c 0x00 0x00 0x0e
+
+# CHECK: get r0, rfsl15
+0x6c 0x00 0x00 0x0f
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