[llvm-commits] [llvm] r118943 - in /llvm/trunk: lib/Target/MBlaze/MBlazeInstrFormats.td lib/Target/MBlaze/MBlazeInstrInfo.td test/MC/MBlaze/mblaze_typea.s

[Wesley Peck]

Author: peckw
Date: Fri Nov 12 17:41:10 2010
New Revision: 118943

URL: http://llvm.org/viewvc/llvm-project?rev=118943&view=rev
Log:
Fixing improperly encoded reverse subtract instructions in MBlaze backend.

Modified:
    llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td
    llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td
    llvm/trunk/test/MC/MBlaze/mblaze_typea.s

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td?rev=118943&r1=118942&r2=118943&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrFormats.td Fri Nov 12 17:41:10 2010
@@ -125,18 +125,17 @@
 
 class TAR<bits<6> op, bits<11> flags, dag outs, dag ins, string asmstr,
           list<dag> pattern, InstrItinClass itin> :
-          MBlazeInst<op,FRRR,outs, ins, asmstr, pattern, itin>
+          TA<op, flags, outs, ins, asmstr, pattern, itin>
 {
-  bits<5> rd;
-  bits<5> rb;
-  bits<5> ra;
+  bits<5> rrd;
+  bits<5> rrb;
+  bits<5> rra;
 
   let Form = FRRRR;
 
-  let Inst{6-10}  = rd;
-  let Inst{11-15} = ra;
-  let Inst{16-20} = rb;
-  let Inst{21-31} = flags;
+  let rd = rrd;
+  let ra = rra;
+  let rb = rrb;
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=118943&r1=118942&r2=118943&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Fri Nov 12 17:41:10 2010
@@ -177,7 +177,7 @@
 
 class ArithR<bits<6> op, bits<11> flags, string instr_asm, SDNode OpNode,
             InstrItinClass itin> :
-            TAR<op, flags, (outs GPR:$dst), (ins GPR:$c, GPR:$b),
+            TAR<op, flags, (outs GPR:$dst), (ins GPR:$b, GPR:$c),
                 !strconcat(instr_asm, "   $dst, $c, $b"),
                 [(set GPR:$dst, (OpNode GPR:$b, GPR:$c))], itin>;
 

Modified: llvm/trunk/test/MC/MBlaze/mblaze_typea.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MBlaze/mblaze_typea.s?rev=118943&r1=118942&r2=118943&view=diff
==============================================================================
--- llvm/trunk/test/MC/MBlaze/mblaze_typea.s (original)
+++ llvm/trunk/test/MC/MBlaze/mblaze_typea.s Fri Nov 12 17:41:10 2010
@@ -81,24 +81,24 @@
 # CHECK:    encoding: [0x80,0x22,0x18,0x00]
             or      r1, r2, r3
 
-# FIXMEC:   rsub
+# CHECK:    rsub
 # BINARY:   000001 00001 00010 00011 00000000000
-# FIXMEC:   encoding: [0x04,0x22,0x18,0x00]
+# CHECK:    encoding: [0x04,0x22,0x18,0x00]
             rsub    r1, r2, r3
 
-# FIXMEC:   rsubc
+# CHECK:    rsubc
 # BINARY:   000011 00001 00010 00011 00000000000
-# FIXMEC:   encoding: [0x0c,0x22,0x18,0x00]
+# CHECK:    encoding: [0x0c,0x22,0x18,0x00]
             rsubc   r1, r2, r3
 
-# FIXMEC:   rsubk
+# CHECK:    rsubk
 # BINARY:   000101 00001 00010 00011 00000000000
-# FIXMEC:   encoding: [0x14,0x22,0x18,0x00]
+# CHECK:    encoding: [0x14,0x22,0x18,0x00]
             rsubk   r1, r2, r3
 
-# FIXMEC:   rsubkc
+# CHECK:    rsubkc
 # BINARY:   000111 00001 00010 00011 00000000000
-# FIXMEC:   encoding: [0x1c,0x22,0x18,0x00]
+# CHECK:    encoding: [0x1c,0x22,0x18,0x00]
             rsubkc  r1, r2, r3
 
 # CHECK:    sext16