[llvm-commits] [llvm] r118925 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td
Jim Grosbach
grosbach at apple.com
Fri Nov 12 13:28:15 PST 2010
Author: grosbach
Date: Fri Nov 12 15:28:15 2010
New Revision: 118925
URL: http://llvm.org/viewvc/llvm-project?rev=118925&view=rev
Log:
Refactor to parameterize some ARM load/store encoding patterns. Preparatory
to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118925&r1=118924&r2=118925&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Nov 12 15:28:15 2010
@@ -491,90 +491,28 @@
let Inst{27-26} = 0b01;
}
-// Pre-indexed loads
-class AI2ldwpr<dag oops, dag iops, Format f, InstrItinClass itin,
- string opc, string asm, string cstr, list<dag> pattern>
- : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
- opc, asm, cstr, pattern> {
- let Inst{20} = 1; // L bit
- let Inst{21} = 1; // W bit
- let Inst{22} = 0; // B bit
- let Inst{24} = 1; // P bit
- let Inst{27-26} = 0b01;
-}
-class AI2ldbpr<dag oops, dag iops, Format f, InstrItinClass itin,
- string opc, string asm, string cstr, list<dag> pattern>
- : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
- opc, asm, cstr, pattern> {
- let Inst{20} = 1; // L bit
- let Inst{21} = 1; // W bit
- let Inst{22} = 1; // B bit
- let Inst{24} = 1; // P bit
- let Inst{27-26} = 0b01;
-}
-
-// Pre-indexed stores
-class AI2stwpr<dag oops, dag iops, Format f, InstrItinClass itin,
- string opc, string asm, string cstr, list<dag> pattern>
- : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
- opc, asm, cstr, pattern> {
- let Inst{20} = 0; // L bit
- let Inst{21} = 1; // W bit
- let Inst{22} = 0; // B bit
- let Inst{24} = 1; // P bit
- let Inst{27-26} = 0b01;
-}
-class AI2stbpr<dag oops, dag iops, Format f, InstrItinClass itin,
- string opc, string asm, string cstr, list<dag> pattern>
+// Pre-indexed load/stores
+class AI2ldstpr<bit isLd, bit opc22, dag oops, dag iops, Format f,
+ InstrItinClass itin, string opc, string asm, string cstr,
+ list<dag> pattern>
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
opc, asm, cstr, pattern> {
- let Inst{20} = 0; // L bit
+ let Inst{20} = isLd; // L bit
let Inst{21} = 1; // W bit
- let Inst{22} = 1; // B bit
+ let Inst{22} = opc22; // B bit
let Inst{24} = 1; // P bit
let Inst{27-26} = 0b01;
}
-// Post-indexed loads
-class AI2ldwpo<dag oops, dag iops, Format f, InstrItinClass itin,
- string opc, string asm, string cstr, list<dag> pattern>
- : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
- opc, asm, cstr,pattern> {
- let Inst{20} = 1; // L bit
- let Inst{21} = 0; // W bit
- let Inst{22} = 0; // B bit
- let Inst{24} = 0; // P bit
- let Inst{27-26} = 0b01;
-}
-class AI2ldbpo<dag oops, dag iops, Format f, InstrItinClass itin,
- string opc, string asm, string cstr, list<dag> pattern>
- : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
- opc, asm, cstr,pattern> {
- let Inst{20} = 1; // L bit
- let Inst{21} = 0; // W bit
- let Inst{22} = 1; // B bit
- let Inst{24} = 0; // P bit
- let Inst{27-26} = 0b01;
-}
-
-// Post-indexed stores
-class AI2stwpo<dag oops, dag iops, Format f, InstrItinClass itin,
- string opc, string asm, string cstr, list<dag> pattern>
- : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
- opc, asm, cstr,pattern> {
- let Inst{20} = 0; // L bit
- let Inst{21} = 0; // W bit
- let Inst{22} = 0; // B bit
- let Inst{24} = 0; // P bit
- let Inst{27-26} = 0b01;
-}
-class AI2stbpo<dag oops, dag iops, Format f, InstrItinClass itin,
- string opc, string asm, string cstr, list<dag> pattern>
+// Post-indexed load/stores
+class AI2ldstpo<bit isLd, bit opc22, dag oops, dag iops, Format f,
+ InstrItinClass itin, string opc, string asm, string cstr,
+ list<dag> pattern>
: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
opc, asm, cstr,pattern> {
- let Inst{20} = 0; // L bit
+ let Inst{20} = isLd; // L bit
let Inst{21} = 0; // W bit
- let Inst{22} = 1; // B bit
+ let Inst{22} = opc22; // B bit
let Inst{24} = 0; // P bit
let Inst{27-26} = 0b01;
}
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118925&r1=118924&r2=118925&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Nov 12 15:28:15 2010
@@ -1540,11 +1540,11 @@
[]>, Requires<[IsARM, HasV5TE]>;
// Indexed loads
-def LDR_PRE : AI2ldwpr<(outs GPR:$Rt, GPR:$Rn_wb),
+def LDR_PRE : AI2ldstpr<1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addrmode2:$addr), LdFrm, IIC_iLoad_ru,
"ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
-def LDR_POST : AI2ldwpo<(outs GPR:$Rt, GPR:$Rn_wb),
+def LDR_POST : AI2ldstpo<1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
(ins GPR:$Rn, am2offset:$offset), LdFrm, IIC_iLoad_ru,
"ldr", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
@@ -1556,11 +1556,11 @@
(ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
"ldrh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
-def LDRB_PRE : AI2ldbpr<(outs GPR:$Rt, GPR:$Rn_wb),
+def LDRB_PRE : AI2ldstpr<1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru,
"ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
-def LDRB_POST : AI2ldbpo<(outs GPR:$Rt, GPR:$Rn_wb),
+def LDRB_POST : AI2ldstpo<1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins GPR:$Rn,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
"ldrb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
@@ -1596,13 +1596,13 @@
// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
-def LDRT : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
+def LDRT : AI2ldstpo<1, 0, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
"ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
let Inst{21} = 1; // overwrite
}
-def LDRBT : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
+def LDRBT : AI2ldstpo<1, 1, (outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
"ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
let Inst{21} = 1; // overwrite
@@ -1641,14 +1641,14 @@
"strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
// Indexed stores
-def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
+def STR_PRE : AI2ldstpr<0, 0, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, am2offset:$offset),
StFrm, IIC_iStore_ru,
"str", "\t$src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb,
(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
-def STR_POST : AI2stwpo<(outs GPR:$base_wb),
+def STR_POST : AI2ldstpo<0, 0, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore_ru,
"str", "\t$src, [$base], $offset", "$base = $base_wb",
@@ -1669,14 +1669,14 @@
[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
GPR:$base, am3offset:$offset))]>;
-def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
+def STRB_PRE : AI2ldstpr<0, 1, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore_bh_ru,
"strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
GPR:$base, am2offset:$offset))]>;
-def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
+def STRB_POST: AI2ldstpo<0, 1, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore_bh_ru,
"strb", "\t$src, [$base], $offset", "$base = $base_wb",
@@ -1699,7 +1699,7 @@
// STRT, STRBT, and STRHT are for disassembly only.
-def STRT : AI2stwpo<(outs GPR:$base_wb),
+def STRT : AI2ldstpo<0, 0, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore_ru,
"strt", "\t$src, [$base], $offset", "$base = $base_wb",
@@ -1707,7 +1707,7 @@
let Inst{21} = 1; // overwrite
}
-def STRBT : AI2stbpo<(outs GPR:$base_wb),
+def STRBT : AI2ldstpo<0, 1, (outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset),
StFrm, IIC_iStore_bh_ru,
"strbt", "\t$src, [$base], $offset", "$base = $base_wb",
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