[llvm-commits] [llvm] r118905 - /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

[Jim Grosbach]

Author: grosbach
Date: Fri Nov 12 11:52:59 2010
New Revision: 118905

URL: http://llvm.org/viewvc/llvm-project?rev=118905&view=rev
Log:
Encoding for ARM LDRSB instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118905&r1=118904&r2=118905&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Nov 12 11:52:59 2010
@@ -700,14 +700,19 @@
               string opc, string asm, list<dag> pattern>
   : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
       opc, asm, "", pattern> {
-  let Inst{4}     = 1;
-  let Inst{5}     = 0; // H bit
-  let Inst{6}     = 1; // S bit
-  let Inst{7}     = 1;
-  let Inst{20}    = 1; // L bit
-  let Inst{21}    = 0; // W bit
-  let Inst{24}    = 1; // P bit
+  bits<14> addr;
+  bits<4> Rt;
   let Inst{27-25} = 0b000;
+  let Inst{24}    = 1; // P bit
+  let Inst{23}    = addr{8};      // U bit
+  let Inst{22}    = addr{13};     // 1 == imm8, 0 == Rm
+  let Inst{21}    = 0; // W bit
+  let Inst{20}    = 1; // L bit
+  let Inst{19-16} = addr{12-9};   // Rn
+  let Inst{15-12} = Rt;           // Rt
+  let Inst{11-8}  = addr{7-4};    // imm7_4/zero
+  let Inst{7-4}   = 0b1101;
+  let Inst{3-0}   = addr{3-0};    // imm3_0/Rm
 }
 class AXI3ldsb<dag oops, dag iops, Format f, InstrItinClass itin,
                string asm, list<dag> pattern>