[llvm-commits] [llvm] r118767 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td
Jim Grosbach
grosbach at apple.com
Wed Nov 10 17:55:59 PST 2010
Author: grosbach
Date: Wed Nov 10 19:55:59 2010
New Revision: 118767
URL: http://llvm.org/viewvc/llvm-project?rev=118767&view=rev
Log:
Encoding for ARM LDRSH and LDRSH_PRE. Cannonicalize operand names.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118767&r1=118766&r2=118767&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Nov 10 19:55:59 2010
@@ -670,14 +670,19 @@
string opc, string asm, list<dag> pattern>
: I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
opc, asm, "", pattern> {
- let Inst{4} = 1;
- let Inst{5} = 1; // H bit
- let Inst{6} = 1; // S bit
- let Inst{7} = 1;
- let Inst{20} = 1; // L bit
- let Inst{21} = 0; // W bit
- let Inst{24} = 1; // P bit
+ bits<14> addr;
+ bits<4> Rt;
let Inst{27-25} = 0b000;
+ let Inst{24} = 1; // P bit
+ let Inst{23} = addr{8}; // U bit
+ let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
+ let Inst{21} = 0; // W bit
+ let Inst{20} = 1; // L bit
+ let Inst{19-16} = addr{12-9}; // Rn
+ let Inst{15-12} = Rt; // Rt
+ let Inst{11-8} = addr{7-4}; // imm7_4/zero
+ let Inst{7-4} = 0b1111;
+ let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AXI3ldsh<dag oops, dag iops, Format f, InstrItinClass itin,
string asm, list<dag> pattern>
@@ -793,14 +798,19 @@
string opc, string asm, string cstr, list<dag> pattern>
: I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
opc, asm, cstr, pattern> {
- let Inst{4} = 1;
- let Inst{5} = 1; // H bit
- let Inst{6} = 1; // S bit
- let Inst{7} = 1;
- let Inst{20} = 1; // L bit
- let Inst{21} = 1; // W bit
- let Inst{24} = 1; // P bit
+ bits<14> addr;
+ bits<4> Rt;
let Inst{27-25} = 0b000;
+ let Inst{24} = 1; // P bit
+ let Inst{23} = addr{8}; // U bit
+ let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
+ let Inst{21} = 1; // W bit
+ let Inst{20} = 1; // L bit
+ let Inst{19-16} = addr{12-9}; // Rn
+ let Inst{15-12} = Rt; // Rt
+ let Inst{11-8} = addr{7-4}; // imm7_4/zero
+ let Inst{7-4} = 0b1111;
+ let Inst{3-0} = addr{3-0}; // imm3_0/Rm
}
class AI3ldsbpr<dag oops, dag iops, Format f, InstrItinClass itin,
string opc, string asm, string cstr, list<dag> pattern>
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118767&r1=118766&r2=118767&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 10 19:55:59 2010
@@ -1516,45 +1516,45 @@
[]>, Requires<[IsARM, HasV5TE]>;
// Indexed loads
-def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
+def LDR_PRE : AI2ldwpr<(outs GPR:$Rt, GPR:$Rn_wb),
(ins addrmode2:$addr), LdFrm, IIC_iLoad_ru,
- "ldr", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
+ "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
-def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
- (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
- "ldr", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
+def LDR_POST : AI2ldwpo<(outs GPR:$Rt, GPR:$Rn_wb),
+ (ins GPR:$Rn, am2offset:$offset), LdFrm, IIC_iLoad_ru,
+ "ldr", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
-def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
+def LDRH_PRE : AI3ldhpr<(outs GPR:$Rt, GPR:$Rn_wb),
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
- "ldrh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
+ "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
-def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
- (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
- "ldrh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
+def LDRH_POST : AI3ldhpo<(outs GPR:$Rt, GPR:$Rn_wb),
+ (ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
+ "ldrh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
-def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
+def LDRB_PRE : AI2ldbpr<(outs GPR:$Rt, GPR:$Rn_wb),
(ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru,
- "ldrb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
+ "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
-def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
- (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
- "ldrb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
+def LDRB_POST : AI2ldbpo<(outs GPR:$Rt, GPR:$Rn_wb),
+ (ins GPR:$Rn,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
+ "ldrb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
-def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
+def LDRSH_PRE : AI3ldshpr<(outs GPR:$Rt, GPR:$Rn_wb),
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
- "ldrsh", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
+ "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
-def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
- (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
- "ldrsh", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
+def LDRSH_POST: AI3ldshpo<(outs GPR:$Rt, GPR:$Rn_wb),
+ (ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
+ "ldrsh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
-def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
+def LDRSB_PRE : AI3ldsbpr<(outs GPR:$Rt, GPR:$Rn_wb),
(ins addrmode3:$addr), LdMiscFrm, IIC_iLoad_bh_ru,
- "ldrsb", "\t$dst, $addr!", "$addr.base = $base_wb", []>;
+ "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
-def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
- (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru,
- "ldrsb", "\t$dst, [$base], $offset", "$base = $base_wb", []>;
+def LDRSB_POST: AI3ldsbpo<(outs GPR:$Rt, GPR:$Rn_wb),
+ (ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_ru,
+ "ldrsb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
// For disassembly only
def LDRD_PRE : AI3lddpr<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
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