[llvm-commits] [llvm] r118738 - in /llvm/trunk/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td

[Jim Grosbach]

Author: grosbach
Date: Wed Nov 10 17:44:32 2010
New Revision: 118738

URL: http://llvm.org/viewvc/llvm-project?rev=118738&view=rev
Log:
Move LDM predicate operand encoding into base clase. Add STM missing STM
encoding bits.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=118738&r1=118737&r2=118738&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Nov 10 17:44:32 2010
@@ -940,9 +940,11 @@
              string asm, string cstr, list<dag> pattern>
   : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
        asm, cstr, pattern> {
+  bits<4> p;
   bits<16> dsts;
   bits<4> Rn;
   bits<2> amode;
+  let Inst{31-28} = p;
   let Inst{27-25} = 0b100;
   let Inst{24-23} = amode;
   let Inst{22}    = 0; // S bit
@@ -954,10 +956,16 @@
              string asm, string cstr, list<dag> pattern>
   : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
        asm, cstr, pattern> {
+  bits<4> p;
   bits<16> srcs;
-  let Inst{20}    = 0; // L bit
-  let Inst{22}    = 0; // S bit
+  bits<4> Rn;
+  bits<2> amode;
+  let Inst{31-28} = p;
   let Inst{27-25} = 0b100;
+  let Inst{24-23} = amode;
+  let Inst{22}    = 0; // S bit
+  let Inst{20}    = 0; // L bit
+  let Inst{19-16} = Rn;
   let Inst{15-0}  = srcs;
 }
 

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118738&r1=118737&r2=118738&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Wed Nov 10 17:44:32 2010
@@ -1185,8 +1185,6 @@
                        IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
                        "ldm${mode}${p}\t$Rn!, $dsts",
                        "$Rn = $wb", []> {
-  bits<4> p;
-  let Inst{31-28} = p;
   let Inst{21}    = 1;
 }
 
@@ -1710,8 +1708,6 @@
                           reglist:$dsts, variable_ops),
                  IndexModeNone, LdStMulFrm, IIC_iLoad_m,
                  "ldm${amode}${p}\t$Rn, $dsts", "", []> {
-  bits<4> p;
-  let Inst{31-28} = p;
   let Inst{21} = 0;
 }
 
@@ -1720,8 +1716,6 @@
                      IndexModeUpd, LdStMulFrm, IIC_iLoad_mu,
                      "ldm${amode}${p}\t$Rn!, $dsts",
                      "$Rn = $wb", []> {
-  bits<4> p;
-  let Inst{31-28} = p;
   let Inst{21} = 1;
 }
 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
@@ -1731,13 +1725,19 @@
 def STM : AXI4st<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
                           reglist:$srcs, variable_ops),
                  IndexModeNone, LdStMulFrm, IIC_iStore_m,
-                 "stm${amode}${p}\t$Rn, $srcs", "", []>;
+                 "stm${amode}${p}\t$Rn, $srcs", "", []> {
+  let Inst{21} = 0;
+}
 
 def STM_UPD : AXI4st<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
                                       reglist:$srcs, variable_ops),
                      IndexModeUpd, LdStMulFrm, IIC_iStore_mu,
                      "stm${amode}${p}\t$Rn!, $srcs",
-                     "$Rn = $wb", []>;
+                     "$Rn = $wb", []> {
+  bits<4> p;
+  let Inst{31-28} = p;
+  let Inst{21} = 1;
+}
 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq
 
 //===----------------------------------------------------------------------===//