[llvm-commits] [llvm] r118648 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Bill Wendling
isanbard at gmail.com
Tue Nov 9 15:28:45 PST 2010
Author: void
Date: Tue Nov 9 17:28:44 2010
New Revision: 118648
URL: http://llvm.org/viewvc/llvm-project?rev=118648&view=rev
Log:
s/std::vector/SmallVector/
Modified:
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118648&r1=118647&r2=118648&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Nov 9 17:28:44 2010
@@ -128,7 +128,7 @@
} Reg;
struct {
- std::vector<unsigned> *Registers;
+ SmallVector<unsigned, 32> *Registers;
} RegList;
struct {
@@ -203,7 +203,7 @@
return Reg.RegNum;
}
- const std::vector<unsigned> &getRegList() const {
+ const SmallVectorImpl<unsigned> &getRegList() const {
assert(Kind == RegisterList && "Invalid access!");
return *RegList.Registers;
}
@@ -258,8 +258,8 @@
void addRegListOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
- const std::vector<unsigned> &RegList = getRegList();
- for (std::vector<unsigned>::const_iterator
+ const SmallVectorImpl<unsigned> &RegList = getRegList();
+ for (SmallVectorImpl<unsigned>::const_iterator
I = RegList.begin(), E = RegList.end(); I != E; ++I)
Inst.addOperand(MCOperand::CreateReg(*I));
}
@@ -325,11 +325,11 @@
}
static ARMOperand *
- CreateRegList(std::vector<std::pair<unsigned, SMLoc> > &Regs,
+ CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(RegisterList);
- Op->RegList.Registers = new std::vector<unsigned>();
- for (std::vector<std::pair<unsigned, SMLoc> >::iterator
+ Op->RegList.Registers = new SmallVector<unsigned, 32>();
+ for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
I = Regs.begin(), E = Regs.end(); I != E; ++I)
Op->RegList.Registers->push_back(I->first);
std::sort(Op->RegList.Registers->begin(), Op->RegList.Registers->end());
@@ -390,8 +390,8 @@
case RegisterList: {
OS << "<register_list ";
- const std::vector<unsigned> &RegList = getRegList();
- for (std::vector<unsigned>::const_iterator
+ const SmallVectorImpl<unsigned> &RegList = getRegList();
+ for (SmallVectorImpl<unsigned>::const_iterator
I = RegList.begin(), E = RegList.end(); I != E; ) {
OS << *I;
if (++I < E) OS << ", ";
@@ -465,8 +465,7 @@
// Read the rest of the registers in the list.
unsigned PrevRegNum = 0;
- std::vector<std::pair<unsigned, SMLoc> > Registers;
- Registers.reserve(32);
+ SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
do {
bool IsRange = Parser.getTok().is(AsmToken::Minus);
@@ -510,7 +509,7 @@
Parser.Lex(); // Eat right curly brace token.
// Verify the register list.
- std::vector<std::pair<unsigned, SMLoc> >::const_iterator
+ SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
RI = Registers.begin(), RE = Registers.end();
unsigned HighRegNum = RI->first;
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