[llvm-commits] [llvm] r118462 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td ARMMCCodeEmitter.cpp

[Bill Wendling]

Author: void
Date: Mon Nov  8 18:30:18 2010
New Revision: 118462

URL: http://llvm.org/viewvc/llvm-project?rev=118462&view=rev
Log:
Revert r118457 and r118458. These won't hold for GPRs.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118462&r1=118461&r2=118462&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Nov  8 18:30:18 2010
@@ -278,7 +278,6 @@
 
 // A list of registers separated by comma. Used by load/store multiple.
 def reglist : Operand<i32> {
-  int NumOperands = 2;
   string EncoderMethod = "getRegisterListOpValue";
   let PrintMethod = "printRegisterList";
 }

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118462&r1=118461&r2=118462&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Nov  8 18:30:18 2010
@@ -378,11 +378,14 @@
 
 unsigned ARMMCCodeEmitter::
 getRegisterListOpValue(const MCInst &MI, unsigned Op,
-                       SmallVectorImpl<MCFixup> &) const {
-  // {12-8} = Rd
-  // {7-0}  = count
-  unsigned Binary = getARMRegisterNumbering(MI.getOperand(Op).getReg()) << 8;
-  Binary |= MI.getOperand(Op + 1).getImm() & 0xFF;
+                       SmallVectorImpl<MCFixup> &Fixups) const {
+  // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
+  // register in the list, set the corresponding bit.
+  unsigned Binary = 0;
+  for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
+    unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
+    Binary |= 1 << regno;
+  }
   return Binary;
 }