[llvm-commits] [llvm] r118446 - /llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

[Bill Wendling]

Author: void
Date: Mon Nov  8 15:28:03 2010
New Revision: 118446

URL: http://llvm.org/viewvc/llvm-project?rev=118446&view=rev
Log:
Add "write back" bit encoding.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=118446&r1=118445&r2=118446&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Nov  8 15:28:03 2010
@@ -80,14 +80,16 @@
                            reglist:$dsts, variable_ops),
                   IndexModeNone, IIC_fpLoad_m,
                   "vldm${amode}${p}\t$Rn, $dsts", "", []> {
-  let Inst{20} = 1;
+  let Inst{21} = 0;             // wback = (W == '1')
+  let Inst{20} = 1;             // Load
 }
 
 def VLDMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
                            reglist:$dsts, variable_ops),
                   IndexModeNone, IIC_fpLoad_m,
                   "vldm${amode}${p}\t$Rn, $dsts", "", []> {
-  let Inst{20} = 1;
+  let Inst{21} = 0;             // wback = (W == '1')
+  let Inst{20} = 1;             // Load
 }
 
 def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
@@ -95,7 +97,8 @@
                       IndexModeUpd, IIC_fpLoad_mu,
                       "vldm${amode}${p}\t$Rn!, $dsts",
                       "$Rn = $wb", []> {
-  let Inst{20} = 1;
+  let Inst{21} = 1;             // wback = (W == '1')
+  let Inst{20} = 1;             // Load
 }
 
 def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
@@ -103,7 +106,8 @@
                       IndexModeUpd, IIC_fpLoad_mu, 
                       "vldm${amode}${p}\t$Rn!, $dsts",
                       "$Rn = $wb", []> {
-  let Inst{20} = 1;
+  let Inst{21} = 1;             // wback = (W == '1')
+  let Inst{20} = 1;             // Load
 }
 } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
 
@@ -113,14 +117,16 @@
                            reglist:$srcs, variable_ops),
                   IndexModeNone, IIC_fpStore_m,
                   "vstm${amode}${p}\t$Rn, $srcs", "", []> {
-  let Inst{20} = 0;
+  let Inst{21} = 0;             // wback = (W == '1')
+  let Inst{20} = 0;             // Store
 }
 
 def VSTMS : AXSI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
                            reglist:$srcs, variable_ops), IndexModeNone,
                    IIC_fpStore_m,
                   "vstm${amode}${p}\t$Rn, $srcs", "", []> {
-  let Inst{20} = 0;
+  let Inst{21} = 0;             // wback = (W == '1')
+  let Inst{20} = 0;             // Store
 }
 
 def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
@@ -128,7 +134,8 @@
                       IndexModeUpd, IIC_fpStore_mu,
                       "vstm${amode}${p}\t$Rn!, $srcs",
                       "$Rn = $wb", []> {
-  let Inst{20} = 0;
+  let Inst{21} = 1;             // wback = (W == '1')
+  let Inst{20} = 0;             // Store
 }
 
 def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
@@ -136,7 +143,8 @@
                       IndexModeUpd, IIC_fpStore_mu,
                       "vstm${amode}${p}\t$Rn!, $srcs",
                       "$Rn = $wb", []> {
-  let Inst{20} = 0;
+  let Inst{21} = 1;             // wback = (W == '1')
+  let Inst{20} = 0;             // Store
 }
 } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq