[llvm-commits] [llvm] r118390 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

[Bill Wendling]

Author: void
Date: Sun Nov  7 18:39:58 2010
New Revision: 118390

URL: http://llvm.org/viewvc/llvm-project?rev=118390&view=rev
Log:
Make RegList an ASM operand so that TableGen will generate code for it. This is
an initial implementation and may change once reglists are fully fleshed out.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=118390&r1=118389&r2=118390&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Sun Nov  7 18:39:58 2010
@@ -282,6 +282,11 @@
   let PrintMethod = "printRegisterList";
 }
 
+def RegListAsmOperand : AsmOperandClass {
+  let Name = "RegList";
+  let SuperClasses = [];
+}
+
 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
 def cpinst_operand : Operand<i32> {
   let PrintMethod = "printCPInstOperand";
@@ -454,7 +459,7 @@
   let PrintMethod = "printLdStmModeOperand";
 }
 
-def ARMMemMode5AsmOperand : AsmOperandClass {
+def MemMode5AsmOperand : AsmOperandClass {
   let Name = "MemMode5";
   let SuperClasses = [];
 }
@@ -465,7 +470,7 @@
                 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
   let PrintMethod = "printAddrMode5Operand";
   let MIOperandInfo = (ops GPR:$base, i32imm);
-  let ParserMatchClass = ARMMemMode5AsmOperand;
+  let ParserMatchClass = MemMode5AsmOperand;
   string EncoderMethod = "getAddrMode5OpValue";
 }