[llvm-commits] [llvm] r118351 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Bill Wendling
isanbard at gmail.com
Sat Nov 6 12:56:04 PDT 2010
Author: void
Date: Sat Nov 6 14:56:04 2010
New Revision: 118351
URL: http://llvm.org/viewvc/llvm-project?rev=118351&view=rev
Log:
Add a RegList (register list) object to ARMOperand. It will be used soon to hold
(surprise!) a list of registers. Register lists are consecutive, so we only need
to record the start register plus the number of registers.
Modified:
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=118351&r1=118350&r2=118351&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Sat Nov 6 14:56:04 2010
@@ -42,7 +42,6 @@
MCAsmParser &Parser;
TargetMachine &TM;
-private:
MCAsmParser &getParser() const { return Parser; }
MCAsmLexer &getLexer() const { return Parser.getLexer(); }
@@ -118,6 +117,7 @@
Immediate,
Memory,
Register,
+ RegisterList,
Token
} Kind;
@@ -138,6 +138,11 @@
bool Writeback;
} Reg;
+ struct {
+ unsigned RegStart;
+ unsigned Number;
+ } RegList;
+
struct {
const MCExpr *Val;
} Imm;
@@ -174,6 +179,9 @@
case Register:
Reg = o.Reg;
break;
+ case RegisterList:
+ RegList = o.RegList;
+ break;
case Immediate:
Imm = o.Imm;
break;
@@ -203,6 +211,11 @@
return Reg.RegNum;
}
+ std::pair<unsigned, unsigned> getRegList() const {
+ assert(Kind == RegisterList && "Invalid access!");
+ return std::make_pair(RegList.RegStart, RegList.Number);
+ }
+
const MCExpr *getImm() const {
assert(Kind == Immediate && "Invalid access!");
return Imm.Val;
@@ -211,6 +224,7 @@
bool isCondCode() const { return Kind == CondCode; }
bool isImm() const { return Kind == Immediate; }
bool isReg() const { return Kind == Register; }
+ bool isRegList() const { return Kind == RegisterList; }
bool isToken() const { return Kind == Token; }
bool isMemory() const { return Kind == Memory; }
@@ -312,6 +326,16 @@
return Op;
}
+ static ARMOperand *CreateRegList(unsigned RegStart, unsigned Number,
+ SMLoc S, SMLoc E) {
+ ARMOperand *Op = new ARMOperand(RegisterList);
+ Op->RegList.RegStart = RegStart;
+ Op->RegList.Number = Number;
+ Op->StartLoc = S;
+ Op->EndLoc = E;
+ return Op;
+ }
+
static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
ARMOperand *Op = new ARMOperand(Immediate);
Op->Imm.Val = Val;
@@ -364,6 +388,19 @@
case Register:
OS << "<register " << getReg() << ">";
break;
+ case RegisterList: {
+ OS << "<register_list ";
+ std::pair<unsigned, unsigned> List = getRegList();
+ unsigned RegEnd = List.first + List.second;
+
+ for (unsigned Idx = List.first; Idx < RegEnd; ) {
+ OS << Idx;
+ if (++Idx < RegEnd) OS << ", ";
+ }
+
+ OS << ">";
+ break;
+ }
case Token:
OS << "'" << getToken() << "'";
break;
More information about the llvm-commits
mailing list