[llvm-commits] [llvm] r118291 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/vbits.ll test/MC/ARM/neon-bitwise-encoding.s
Owen Anderson
resistor at mac.com
Fri Nov 5 14:39:03 PDT 2010
On Nov 5, 2010, at 2:35 PM, Bob Wilson wrote:
> This looks good. You're still going to fix isNEONModifiedImm to distinguish VBIC/VORR, right?
I'm not sure it needs to. There seem to be only two cases: all types allowed (isVMOV == true) and only i16 and i32 allows (isVMOV == false). Are there other modified immediate instructions that have some different type combination they allow?
--Owen
> On Nov 5, 2010, at 12:27 PM, Owen Anderson wrote:
>
>> Author: resistor
>> Date: Fri Nov 5 14:27:46 2010
>> New Revision: 118291
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=118291&view=rev
>> Log:
>> Add codegen and encoding support for the immediate form of vbic.
>>
>> Modified:
>> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>> llvm/trunk/lib/Target/ARM/ARMISelLowering.h
>> llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> llvm/trunk/test/CodeGen/ARM/vbits.ll
>> llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=118291&r1=118290&r2=118291&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Nov 5 14:27:46 2010
>> @@ -673,8 +673,10 @@
>> setTargetDAGCombine(ISD::SUB);
>> setTargetDAGCombine(ISD::MUL);
>>
>> - if (Subtarget->hasV6T2Ops())
>> + if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
>> setTargetDAGCombine(ISD::OR);
>> + if (Subtarget->hasNEON())
>> + setTargetDAGCombine(ISD::AND);
>>
>> setStackPointerRegisterToSaveRestore(ARM::SP);
>>
>> @@ -4443,6 +4445,36 @@
>> return SDValue();
>> }
>>
>> +static SDValue PerformANDCombine(SDNode *N,
>> + TargetLowering::DAGCombinerInfo &DCI) {
>> + // Attempt to use immediate-form VBIC
>> + BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
>> + DebugLoc dl = N->getDebugLoc();
>> + EVT VT = N->getValueType(0);
>> + SelectionDAG &DAG = DCI.DAG;
>> +
>> + APInt SplatBits, SplatUndef;
>> + unsigned SplatBitSize;
>> + bool HasAnyUndefs;
>> + if (BVN &&
>> + BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
>> + if (SplatBitSize <= 64) {
>> + EVT VbicVT;
>> + SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
>> + SplatUndef.getZExtValue(), SplatBitSize,
>> + DAG, VbicVT, VT.is128BitVector(), false);
>> + if (Val.getNode()) {
>> + SDValue Input =
>> + DAG.getNode(ISD::BIT_CONVERT, dl, VbicVT, N->getOperand(0));
>> + SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
>> + return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vbic);
>> + }
>> + }
>> + }
>> +
>> + return SDValue();
>> +}
>> +
>> /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
>> static SDValue PerformORCombine(SDNode *N,
>> TargetLowering::DAGCombinerInfo &DCI,
>> @@ -5066,6 +5098,7 @@
>> case ISD::SUB: return PerformSUBCombine(N, DCI);
>> case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
>> case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
>> + case ISD::AND: return PerformANDCombine(N, DCI);
>> case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
>> case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
>> case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=118291&r1=118290&r2=118291&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Fri Nov 5 14:27:46 2010
>> @@ -165,7 +165,9 @@
>> BFI,
>>
>> // Vector OR with immediate
>> - VORRIMM
>> + VORRIMM,
>> + // Vector AND with NOT of immediate
>> + VBICIMM
>> };
>> }
>>
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=118291&r1=118290&r2=118291&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Fri Nov 5 14:27:46 2010
>> @@ -72,6 +72,7 @@
>> def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
>> SDTCisVT<2, i32>]>;
>> def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
>> +def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
>>
>> def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
>>
>> @@ -3308,13 +3309,13 @@
>> let Inst{9} = SIMM{9};
>> }
>>
>> -def VORRiv2i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 0, 0, 1,
>> +def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
>> (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
>> IIC_VMOVImm,
>> "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
>> [(set DPR:$Vd,
>> (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
>> - let Inst{11-9} = SIMM{11-9};
>> + let Inst{10-9} = SIMM{10-9};
>> }
>>
>> def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
>> @@ -3326,13 +3327,13 @@
>> let Inst{9} = SIMM{9};
>> }
>>
>> -def VORRiv4i32 : N1ModImm<1, 0b000, {?,?,?,1}, 0, 1, 0, 1,
>> +def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
>> (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
>> IIC_VMOVImm,
>> "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
>> [(set QPR:$Vd,
>> (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
>> - let Inst{11-9} = SIMM{11-9};
>> + let Inst{10-9} = SIMM{10-9};
>> }
>>
>>
>> @@ -3348,6 +3349,42 @@
>> [(set QPR:$dst, (v4i32 (and QPR:$src1,
>> (vnotq QPR:$src2))))]>;
>>
>> +def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
>> + (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
>> + IIC_VMOVImm,
>> + "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
>> + [(set DPR:$Vd,
>> + (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
>> + let Inst{9} = SIMM{9};
>> +}
>> +
>> +def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
>> + (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
>> + IIC_VMOVImm,
>> + "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
>> + [(set DPR:$Vd,
>> + (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
>> + let Inst{10-9} = SIMM{10-9};
>> +}
>> +
>> +def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
>> + (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
>> + IIC_VMOVImm,
>> + "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
>> + [(set QPR:$Vd,
>> + (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
>> + let Inst{9} = SIMM{9};
>> +}
>> +
>> +def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
>> + (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
>> + IIC_VMOVImm,
>> + "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
>> + [(set QPR:$Vd,
>> + (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
>> + let Inst{10-9} = SIMM{10-9};
>> +}
>> +
>> // VORN : Vector Bitwise OR NOT
>> def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
>> (ins DPR:$src1, DPR:$src2), N3RegFrm, IIC_VBINiD,
>>
>> Modified: llvm/trunk/test/CodeGen/ARM/vbits.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vbits.ll?rev=118291&r1=118290&r2=118291&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/ARM/vbits.ll (original)
>> +++ llvm/trunk/test/CodeGen/ARM/vbits.ll Fri Nov 5 14:27:46 2010
>> @@ -525,3 +525,23 @@
>> %tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
>> ret <16 x i8> %tmp3
>> }
>> +
>> +define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
>> +; CHECK: v_bicimm:
>> +; CHECK-NOT: vmov
>> +; CHECK-NOT vmvn
>> +; CHECK: vbic
>> + %tmp1 = load <8 x i8>* %A
>> + %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
>> + ret <8 x i8> %tmp3
>> +}
>> +
>> +define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
>> +; CHECK: v_bicimmQ:
>> +; CHECK-NOT: vmov
>> +; CHECK-NOT: vmvn
>> +; CHECK: vbic
>> + %tmp1 = load <16 x i8>* %A
>> + %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
>> + ret <16 x i8> %tmp3
>> +}
>>
>> Modified: llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s?rev=118291&r1=118290&r2=118291&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s (original)
>> +++ llvm/trunk/test/MC/ARM/neon-bitwise-encoding.s Fri Nov 5 14:27:46 2010
>> @@ -26,6 +26,10 @@
>> vbic d16, d17, d16
>> @ CHECK: vbic q8, q8, q9 @ encoding: [0xf2,0x01,0x50,0xf2]
>> vbic q8, q8, q9
>> +@ CHECK: vbic.i32 d16, #0xFF000000 @ encoding: [0x3f,0x07,0xc7,0xf3]
>> + vbic.i32 d16, #0xFF000000
>> +@ CHECK: vbic.i32 q8, #0xFF000000 @ encoding: [0x7f,0x07,0xc7,0xf3]
>> + vbic.i32 q8, #0xFF000000
>>
>> @ CHECK: vorn d16, d17, d16 @ encoding: [0xb0,0x01,0x71,0xf2]
>> vorn d16, d17, d16
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20101105/7b8a9a5e/attachment.html>
More information about the llvm-commits
mailing list