[llvm-commits] [llvm] r118199 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

[Jim Grosbach]

Author: grosbach
Date: Wed Nov  3 17:03:20 2010
New Revision: 118199

URL: http://llvm.org/viewvc/llvm-project?rev=118199&view=rev
Log:
trailing whitespace

Modified:
    llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=118199&r1=118198&r2=118199&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Nov  3 17:03:20 2010
@@ -255,7 +255,7 @@
   // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
   // shifted. The second is either Rs, the amount to shift by, or reg0 in which
   // case the imm contains the amount to shift by.
-  // 
+  //
   // {3-0} = Rm.
   // {4}   = 1 if reg shift, 0 if imm shift
   // {6-5} = type
@@ -349,7 +349,7 @@
                                                       unsigned Op) const {
   const MCOperand &Reg = MI.getOperand(Op);
   const MCOperand &Imm = MI.getOperand(Op + 1);
-  
+
   unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
   unsigned Align = 0;